Senior Research Scientist, Intel Labs, hongbo.rong@intel.com
Current Researches
- AI for microarchitectures
Champion of Intel's Research Velocity Challenge 2017.
POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations.
Xiaochen Hao, Hongbo Rong, Mingzhe Zhang, Ce Sun, Hong Jiang, Yun Liang. FPGA, 2024. [Open source][PDF]
Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAs
Xiaochen Hao, Mingzhe Zhang, Ce Sun, Zhuofu Tao, Hongbo Rong, Yu Zhang, Lei He, Eric Petit, Wenguang Chen, Yun Liang. FCCM, 2023. [Open source][PDF]
FCCM tutorial: Productive Construction of High-Performance Systolic Arrays on FPGAs [Slides]
Organizers: Zhiru Zhang, Jason Cong, Hongbo Rong
Programmatic Control of a Compiler for Generating High-performance Spatial Hardware
Hongbo Rong. https://arxiv.org/abs/1711.07606 .
SuSy: a programming model for productive construction of high-performance systolic arrays on FPGAs.
Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher Hughes, and Pradeep Dubey. 2020. ICCAD'20. [PDF][Video]
T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations
Nitish Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David Albonesi,Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher Hughes,Timothy Mattson, Pradeep Dubey. FCCM, 2019. [PDF][Slides][Video]
Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations
Nitish Srivastava, Hanchen Jin, Shaden Smith, Hongbo Rong, David Albonesi, Zhiru Zhang. HPCA, 2020. [PDF][Slides][Video]
Expressing Sparse Matrix Computations for Productive Performance on Spatial Architectures
Hongbo Rong. https://arxiv.org/abs/1810.07517
Systolic Computing on GPUs for Productive Performance
Hongbo Rong, Xiaochen Hao, Yun Liang, Lidong Xu, Hong H Jiang, Pradeep Dubey. [PDF]
Building Application-Specific Overlays on FPGAs with High-Level Customizable IPs
Hongbo Rong. [PDF]
Programming and Synthesis for Software-Defined FPGA Acceleration: Status and Future Prospects
Yi-Hsiang Lai, Ecenur Ustun, Shaojie Xiang, Zhenman Fang, Hongbo Rong, Zhiru Zhang, ACM Transactions on Reconfigurable Technology and Systems (TRETS), Dec. 2021. [PDF]
Teaching
Register Allocation, Peking Univ. 6/4/2021. [Slides]
Recognitions
SRC Mahboob Khan Outstanding Liaison Award, 2020
Invention awards of Intel: Distinguished Invention Award 2017, High-5 Award 2013
Champion of Intel's Research Velocity Challenge 2017
Nomination for Best Paper Finalist at SC'16
Best Paper Award at CGO'14
Best Paper Award at CGO'04
Recent Services
Associate Editor, ACM Transactions on Reconfigurable Technology and Systems, 2019~
Liaison, Semiconductor Research Company, 2019~
Guest Editor, IEEE Circuits and Systems, Special Issue on FPGA Evolution, 21(2), 2021.
Program committee member, LATTE ’21 Workshop on Languages, Tools, and Techniques for Accelerator Design
Technical champion, Cornell/UCLA of Intel-NSF Computer Assisted Programming for Heterogeneous Architectures (CAPA) research, 2017~2020.
External review committee member, PACT 2019 28th International Conference on Parallel Architectures and Compilation Techniques
Session co-host, Compilation for Spatial Computing Architectures at 2019 Asilomar Conference on Signals, Systems, and Computers
Previous Research
Sparso: Context-driven Optimizations of Sparse Linear Algebra
Hongbo Rong, Jongsoo Park, Lingxiang Xiang, Todd Anderson, Mikhail Smelyanskiy. PACT, 2016. [PDF] [Open Source]
Automating Wavefront Parallelization for Sparse Matrix Codes.
Anand Venkat, Mahdi Soltan Mohammadi, Jongsoo Park, Hongbo Rong, Rajkishore Barik, Michelle Mills Strout, Mary Hall. SC, 2016. Nominated as a Best Paper Finalist. [PDF]
ProductiveC: Enabling High Productivity in C-Family Languages
Hongbo Rong
Computing Frontiers (CF), 2015. [PDF]
Just-in-time Software Pipelining
Hongbo Rong, Hyunchul Park, Youfeng Wu, Cheng Wang.
International Symposium on Code Generation and Optimization (CGO), 2014. Best Paper Award. [PDF][PPT]
Allocating Rotating Registers by Scheduling
Hongbo Rong, Hyunchul Park, Cheng Wang, Youfeng Wu.
International Symposium on Microarchitecture (MICRO), 2013. [PDF][PPT]
Tree Register Allocation
Hongbo Rong. Symposium on Microarchitecture (MICRO), 2009. [PDF][PPT]
Single-Dimension Software Pipelining for Multi-Dimensional Loops
Hongbo Rong, Zhizhong Tang, R. Govindarajan, Alban Douillet, Guang R. Gao.
International Symposium on Code Generation and Optimization (CGO), 2004. Best Paper Award. [PDF]
ACM Transactions on Architecture and Code Optimization (TACO), 2007. [PDF]
Register Allocation for Software Pipelined Multi-dimensional Loops
Hongbo Rong, Alban Douillet, Guang R. Gao.
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2005. [PDF]
ACM Transactions on Programming Languages and Systems (TOPLAS), 2008. [PDF]
Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops.
Hongbo Rong, Alban Douillet, R. Govindarajan, Guang R. Gao. International Symposium on Code Generation and Optimization ( CGO), 2004. [PDF]
Book chapter
Advances in Software Pipelining.
Hongbo Rong, R. Govindarajan.
Chapter 20 in Compiler Design Handbook: Optimizations and Machine Code Generation. Srikant and Shankar Eds. 2nd Edition. 2007
Product components
Visual C++ compiler
Type system and C++ optimizations.
Phoenix compiler
Local scheduler and dependence graph.
Code quality analysis.
Warning phase.
Bartok compiler
Card marking writer barrier
Patents
Method and apparatus for supporting programmatic control of a compiler for generating high-performance spatial hardware
Hongbo Rong. Patent number: 1116354
FPGA tracing as a debugging aid for software programmers
Hongbo Rong. Distinguished Invention Award of Intel. 2017
Methods, Systems and Apparatus to Optimize Sparse Matrix Applications
Hongbo Rong, Jongsoo Park, Mikhail Smelyanskiy, Geoff Lowney. US Patent, No. 9720663
Technologies for Low-level Composable High Performance Computing Libraries
Hongbo Rong, Peng Tu, Tatiana Shpeisman, Hai Liu, Todd A. Anderson, Youfeng Wu, Paul M. Petersen, Victor W. Lee, P. G. Lowney, Arch D. Robison, Cheng Wang. US Patent, No. 9690552
Allocation of Alias Registers in a Pipelined Schedule
Hongbo Rong, Cheng Wang, Hyunchul Park, Youfeng Wu. US Patent, No. 9495168
Software Pipelining at Runtime
Hongbo Rong, Hyunchul Park, Youfeng Wu. US Patent, No. 9239712
Dynamic Optimization of Pipelined Software
Hyunchu Park, Hongbo Rong, Youfeng Wu. US Patent, No. 9170792
Method and Products for Processing Loop Nests
Hongbo Rong, Guang R. Gao, Alban Douillet, R. Govindarjan. US Patent, No. 7631305.
Conjugate Code Generation for Efficient Dynamic Optimizations
Hongbo Rong, Hyunchul Park, Cheng Wang, Youfeng Wu. US patent number: 10268497
Technologies for Automatic Reordering of Sparse Matrices
Hongbo Rong, Jongsoo Park, Todd A. Anderson. US patent number: 10310826
Technologies for Optimizing Sparse Matrix Code with Field-Programmable Gate Arrays
Hongbo Rong, Gilles A. Pokam. US patent number: 9977663
Instruction and Logic to Monitor Loop Trip Count and Remove Loop Optimizations
Jaewoong Chung, Hyunchul Park, Hongbo Rong, Cheng Wang, Youfeng Wu. US Patent. No.9715388.
Co-designed Dynamic Language Accelerator for a Processor
Cheng Wang, Youfeng Wu, Hongbo Rong, Hyunchul Park. US Patent. No. 9542211
Technologies for Persistent Memory Programming
Xipeng Shen, Youfeng Wu, Cheng Wang, Hyunchul Park, Hongbo Rong. US patent number: 9940229
软件流水的移位旋转式硬件控制装置.
容红波, 汤志忠. 中国专利, 2003. No. 00133535.9.