Hong-fu Chou  received the M.S. and Ph.D. degree in communication engineering from National Taiwan University, Taipei, Taiwan in 2006 and 2013, respectively. He is a Postdoctoral Fellow with the School of Computer Science, The University of Auckland, from 2016 to 2020 and currently with Interdisciplinary Centre for Security, Reliability and Trust (SnT), University of Luxembourg. His research interests include digital circuit design, VLSI, FPGA implementation, quantum cryptography and physical layer security.  

He is a researcher and engineer specializing in signal processing, machine learning, and communication systems, particularly within the context of satellite networks and onboard Earth observation. Their work focuses on developing efficient FPGA-based edge AI systems, joint source-channel coding, and AI-integrated semantic inference models for enhanced data transmission and analysis. They have also contributed to research on quantum key distribution networks, millimeter wave communications, and high-frequency trading systems.

Key Research Themes 

• Semantic Task-Oriented Communication: Emphasizing the precision of transmitted data to convey "actionable meaning" rather than just raw bits. This includes:

  • Integrating Discrete Task-Oriented Joint Source-Channel Coding (DT-JSCC) and Semantic Data Augmentation (SA).

  • Reducing communication overhead and improving efficiency specifically for 6G satellite networks.

  • Applying Explainable AI (XAI) principles to ensure transparent, ethical decision-making in critical areas like disaster response and agricultural monitoring.

• Edge AI Integration: Exploring the convergence of AI and edge computing to enhance data processing, privacy, and latency. Focus areas include:

  • Generative AI for resource-limited environments, specifically for real-time IoT and robotics.

  • Applications in autonomous vehicles and healthcare, such as AI-driven diagnostics and drug discovery.

  • Establishing ethical frameworks and bias mitigation for privacy-preserving edge AI.

• Advanced Error-Resilient Compression Frameworks: Developing robust and efficient communication methods for noisy environments. This involves:

  • Combining Large Language Models (LLMs) with error correction codes (ECC) like LDPC or Polar codes for high compression efficiency.

  • Utilizing Deep Learning-Augmented ECC, such as Error Correction Code Transformers (ECCT), to dynamically adapt to varying channel conditions.

  • Creating semantic resilience across multimodal data (images and video) by leveraging LLMs for temporal modeling and feature extraction.

• Physical Layer Security: Innovating applications to empower autonomous systems and robotics while ensuring secure and reliable operations in real-time.

6G Wireless Precoding and Signal Processing

• Scalable HBF Precoding: I have developed scalable and latency-aware Hybrid Beamforming (HBF) precoding designs specifically for Low Earth Orbit (LEO) satellite communications, which are foundational for 6G Non-Terrestrial Networks (NTN).

• Physical Layer Security: My work innovates at the physical layer to empower autonomous systems, using edge AI to enhance security and reliability in real-time environments.

• Joint Source-Channel Coding (JSCC): I research the evolution and prototyping of JSCC systems, which are essential for the efficient transmission of semantic data in future 6G architectures.

Hardware Implementation and System Optimization

• FPGA-Based Edge AI: I specialize in the "hands-on" engineering required to implement complex algorithms on hardware, such as developing efficient FPGA-based systems for real-time sensing and fault detection.

• Resource-Constrained Optimization: A core part of my research involves optimizing AI and communication frameworks for memory and energy efficiency, ensuring they are suitable for edge devices in the space and fintech sectors.

• Hardware-Software Co-Design: My teaching and research portfolio emphasizes the integration of hardware-software co-design, leveraging over 15 years of experience in FPGA/ASIC design to support high-performance computing and SoC architecture.

• Error-Resilient Architectures: I explore the implementation of advanced error correction mechanisms (like LDPC or Polar codes) combined with probabilistic modeling to achieve high compression efficiency and noise resilience.