HOME

Profile

Hiromu Miyazaki

Research Division 3, Sony Semiconductor Solutions Corporation

E-mail : Hiromu.Miyazaki (at) sony.com

E-mail : hiromu8811@gmail.com

Work experience

Research Division 3, Sony Semiconductor Solutions Corporation (2022/10 - )

R&D Center, Sony Group Corporation (2021/04 - 2022/09)

Academic background

Master of Engineering in Computer science, Department of Computer Science, School of Computing, Tokyo Institute of Technology, Japan, March 2021

Bachelor of Engineering in Department of Computer Science, School of Engineering, Tokyo Institute of Technology, Japan, March 2019

Associations

The Institute of Electronics, Information and Communication Engineers (IEICE), Member

My Research area

・Computer Architecture

・Processor System

・FPGA

・RISC-V

Research papers

Journal

Hiromu MIYAZAKI, Takuto KANAMORI, Md Ashraful ISLAM, Kenji KISE, RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining, IEICE Transactions on Information and Systems, 2020, Volume E103.D, Issue 12, Pages 2494-2503, Released December 01, 2020, Online ISSN 1745-1361, Print ISSN 0916-8532.

International Conference

Hiromu Miyazaki, Junya Miura, and Kenji Kise. 2019. An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA. In The 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2019), June 6–7, 2019, Nagasaki, Japan.

Technical Committee

Hiromu Miyazaki, Junya Miura, and Kenji Kise, "Efficient Instruction Fetch Architectures for a RISC-V Soft Processor", IEICE Technical Report, Vol. 119, No. 18, RECONF2019-1, pp. 1-6, May 2019.

Junya Miura, Hiromu Miyazaki, and Kenji Kise, "Design and implementation of a RISC-V computer system running Linux in Verilog HDL", IEICE Technical Report, Vol. 119, No. 373, VLD2019-72, CPSY2019-70, RECONF2019-62, pp. 117-122, January 2020.

Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, and Kenji Kise, "Design and implementation of a RISC-V soft processor adopting five-stage pipelining", IEICE Technical Report, Vol. 119, No. 373, VLD2019-73, CPSY2019-71, RECONF2019-63, pp. 123-128, January 2020.

Takuto Kanamori, Hiromu Miyazaki, Kenji Kise, "Design and implementation of a RISC-V soft processor targeting on FPGA-based embedded systems", SIG Technical Reports, 2020-EMB-54-1, pp. 1-8, June 2020.

Katsunoshin Matsui, Hiromu Miyazaki, Kazuki Nakano, and Kenji Kise, "An implementation of an object detection algorhythm on Vitis AI and Winning a prize in the 2nd AI Edge," IEICE Technical Report, Vol. 120, No. 168, RECONF2020-23, pp. 25-29, September 2020.

Preprint

Junya Miura, Hiromu Miyazaki, Kenji Kise: A portable and Linux capable RISC-V computer system in Verilog HDL, arXiv:2002.03576 [cs.AR] (2020-02-10).

Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise: RVCoreP : An optimized RISC-V soft processor of five-stage pipelining, arXiv:2002.03568 [cs.AR] (2020-02-10).

Md Ashraful Islam, Hiromu Miyazaki, and Kenji Kise: RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors, arXiv:2010.16171 [cs.AR] (2020-10-30).

Takuto Kanamori, Hiromu Miyazaki, Kenji Kise: RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions, arXiv:2011.11246 [cs.AR] (2020-11-23).

Thesis

Hiromu Miyazaki, "RISC-Vソフトプロセッサの命令フェッチアーキテクチャ", Bachelor thesis, Department of Computer Science, School of Engineering, Tokyo Institute of Technology, March 2019.

Hiromu Miyazaki, "FPGA向けの最適化手法を用いた5段パイプラインのRISC-Vソフトプロセッサ", Master thesis, Department of Computer Science, School of Computing, Tokyo Institute of Technology, Japan, March 2021.

Research projects

RVCore Project

The RVCore Project is a research and development project of the RISC-V soft processor highly optimized for FPGAs.

Link : https://www.arch.cs.titech.ac.jp/wk/rvcore/doku.php

RVSoC Project

The RVSoC Project is a research and development project of the RISC-V computer system targeting FPGAs in Verilog HDL.

Link : https://www.arch.cs.titech.ac.jp/wk/rvsoc/doku.php

Contest

2nd AI Edge Contest

Team ArchLab : 3rd place in the performance category

Link about the source code : https://github.com/ArchLab-Edge-AI/AI_edge_contest

Link about the contest : https://www.meti.go.jp/english/press/2019/1118_002.html