Above is a picture of me presenting my poster titled 'Silent Data Corruptions in UCIe Chiplets via Fault Injections' at the semi-annual Center for Advanced Electronics through Machine Learning (CAEML) meeting.
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About Me
About Me
Doctoral Student in Computer Engineering at North Carolina State University
Hello, my name is Harshvadan Mihir, and I'm a second-year Ph.D. student in the Department of Electrical and Computer Engineering (ECE) at NC State University. I work at the Hardware Cyberthreat Research (HECTOR) lab under Dr. Aydin Aysu's mentorship, where our research involves tackling issues pertinent to Hardware Security at various fronts.
I work on physical Fault Injection Attacks (FIAs) on various edge AI/ML implementations to assess model inference behavior under various faulty conditions and identify critical vulnerabilities, and come up with effective mitigation strategies that involve minimal to no hardware overhead.
Education
Education
Ph.D., Computer Engineering, North Carolina State University 2024 - 2029 (Expected)
Coursework: ASIC and FPGA Design, Microprocessor Architecture, Cryptography and Hardware Security, ASIC Verification, Parallel Computing, Architecture of Data Parallel Processors (GPUs), Operating Systems
M.S., Computer Engineering, North Carolina State University 2022 - 2024 (GPA: 3.9/4.0)
B.Tech, Electronics and Communication Engineering, Institute of Technology, Nirma University 2018 - 2022
Skills
Skills
My research focuses on the intersection of Hardware Security, Microarchitecture, and AI/ML Systems, with a specialized emphasis on fault-tolerant design and vulnerability assessment. My current work involves:
Fault Injection & Microarchitectural Security: Investigating the resilience of RISC-V architectures against physical attacks and identifying critical vulnerabilities in data and control-flow integrity through pre-silicon simulation and post-silicon validation using clock and voltage glitching.
Secure Chiplet & AI Interconnects: Analyzing the security landscape of next-generation AI hardware, specifically focusing on the UCIe (Universal Chiplet Interconnect Express) protocol. My work involves modeling threat vectors in die-to-die communication and developing methods to bypass integrity checks in high-performance inference pipelines.
Hardware Emulation & Testbed Development: Designing FPGA-based emulation platforms (including multi-board SAKURA-X setups) to facilitate cross-device communication and fault characterization. This includes implementing digital IPs for emerging protocols to study malicious behavior in controlled, real-world hardware environments.
Publications
Publications
CRAFT: Characterizing and root-causing fault injection threats at pre-silicon In Proceedings of the 14th International Workshop on Hardware and Architectural Support for Security and Privacy. (Best Paper Award) Access here.
Contact Information
Contact Information
Email: hmihir@ncsu.edu
Phone: +1 (984) 286-7528
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