[Log #1, 6 Feb. 2021]: Read chapters 1-3 of Free Range VHDL. Successfully installed GHDL and GTKWave, referencing tutorial video provided on CPE-487 course GitHub repo. Successfully wrote "half-adder" VHDL program and tested results with GTKWave.
[Log #2, 12 Feb. 2021]: Reviewed chapters 4-9 of Free Range VHDL. Partnered with Amein A. for FPGA project. Planning to do some VHDL examples to prepare for FPGA term project.
[Log #3, 21 Feb. 2021]: Reviewed chapters 10-12 of Free Range VHDL. Did several Ch.4 practice problems by hand. Was unsuccessful in implementing VHDL code for a Ch. 4 example using GHDL. Files were uploaded to GitHub. Obtained Nexys A7-100T and a Keypad Pmod. Successfully installed Xilinx Vivado HLS WebPACK.
[Log #4, 28 Feb. 2021]: Completed Lab 1. Modified some of Lab 1 "leddec.vhd" code to produce different decoder outputs. Need to work more on "hexcounter.vhd" code.
[Log #5, 8 Mar. 2021]: Worked more on "hexcounter.vhd" code. Successfully implemented "hex4counter.vhd" code and modified it to output counter in Big-Endian format rather than the o9riginal Little-Endian format (results on GitHub). Discussed potential final project ideas with team members.
[Log #6, 15 Mar. 2021]: Collaborated with team in brainstorming more ideas for final project. Considered different methods of approach to final project idea. Set up GitHub repo folder for resources, ideas, and code to build on final project.
[Log #7, 22 Mar. 2021]: Worked on Lab 4. Successfully completed all base modifications. Attempted and failed to implement negative/signed numbers into Lab 4 "HexCalc." May attempt to implement at a later date.
[Log #8, 25 Mar. 2021]: Began work on final project. Successfully implemented VHDL file using code from FPGA4student. Next step would be to implement "proof of concept" function by displaying the bits that the VHDL code reads. Group will work on potentially implementing "leddec" project file to display these bits.
[Log #9, 4 April 2021]: Ran into problems implementing leddec display for file reading code. Problems are described on my GitHub markdown here . Will continue to pursue other avenues regarding this project. Considering moving project to it's own repository.
[Log #10, 9 May 2021]: Included BRAM IP Core into project to no avail. Project was not successfully completed. Details in regards to project progress, what we accomplished, and what we learned could by found on my GitHub linked above.