Eui-Cheol Yun
Eui-Cheol Yun
Mar. 2024 - Present
Ph.D Program School of Semiconductor Engineering, Chungbuk National University, Cheongju, Republic of Korea.
(GPA: 4.46 / 4.5)
Mar. 2018 - Feb. 2024
B.S. School of Electronic Engineering, Chungbuk National University, Cheongju, Republic of Korea.
(GPA: 3.98 / 4.5)
Fabrication Process of Semiconductor Devices
Reliability of Semiconductor Devices
Device Fabrication Processing
[6] Mask Aligner
[5] Thermal Evaproator
[4] Reactive Ion Etching (RIE)
[3] Rapid Thermal Process (RTP)
[2] Plasma Enhanced Deuterium Annealing System (PEDA)
[1] Deuterium Annealing System (RDA & LTDA)
Device Characterization
[4] Ellipsometer
[3] Surface Profiler (Alpha Step)
[2] Device Parameter Analyzer (Keithley 4200A, B1500A)
[1] Probe Station
Software
[1] TCAD Simulation (Sentaurus, Atlas, Athena)
[14] M.-K. Lee, H.-J. Park, E.-C. Yun, T.-H. Kil, J.-W. Yeon, M.-W. Kim, and J.-Y. Park*, "Investigation of Nanosheet FETs with Embedded Gates for Enhanced DC Performance", Silicon, in press. [ Website ]
[13] S.-M. Kang, H.-J. Park, E.-C. Yun, D.-E. Bang, M.-S. Kim*, and J.-Y. Park*, "Dual-Parameter Variable Physically Unclonable Function (PUF) for Multi-level Cell Silicon MOSFETs", ACS Appl. Electron. Mater., vol. 8, no. 6, pp. 2322–2331, Mar. 2026. [ Website ]
[12] D. Sohn, M.-K. Lee, J.-W. Yeon, M.-W. Kim, T.-H. Kil, E.-C. Yun, H.-J. Park, and J.-Y. Park*, "V-Notch Shaped Contact Design in Nanosheet FETs for Enhancing Chip Performance", IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. xx, no. x, pp. xxxx–xxxx, in press. [ Website ]
[11] M.-K. Lee, D.-E. Bang, S.-J. Chang, H.-J. Park, E.-C. Yun, S.-M. Kang, M.-W. Kim, D. Sohn, and J.-Y. Park*, "Rapid Hydrogen Annealing for Enhanced Device Performance and Reduced Thermal Budget", Semicond. Sci. Technol., vol. 41, no. 2, p. 025012, Feb. 2026. [ Website ]
[10] D. Sohn, M.-K. Lee, D.-E. Bang, H.-J. Park, E.-C. Yun, S.-M. Kang, M.-W. Kim, H. Jeon*, and J.-Y. Park*, "Wrap-Around Word-Line DRAM Cell Transistor Enabling Enhanced Read/Write Speed", IEEE Trans. Electron Devices, 73, no. 1, pp. 271–278, Jan. 2026. [ Website ]
[9] E.-C. Yun, H.-J. Park, M.-K. Lee, T.-H. Kil, J.-W. Yeon, M.-W. Kim, D. Sohn, and J.-Y. Park*, "Demonstration of Rapid Deuterium Annealing for High-Performance MOSFETs with Reduced Thermal Budget", IEEE Trans. Electron Devices, vol. 73, no. 1, pp. 707–711, Jan. 2026. [ Website ]
[8] D.-E. Bang, M.-K. Lee, E.-C. Yun, T.-H. Kil, H.-J. Park, J.-W. Yeon, M.-W. Kim, S.-J. Jeon, A-Y. Kim, and J.-Y. Park*, "Junction Depth Optimization in Trench Gate Nanosheet FETs for Reduced Off-State Current", Silicon, vol. 17, pp. 3565–3572, Nov. 2025. [ Website ]
[7] H.-J. Park, M.-K. Lee, E.-C. Yun, D. Sohn, M.-W. Kim, S.-M. Kang, H. Jeon, and J.-Y. Park*, "Investigation of Inner Spacer-Less Nanosheet FETs from an Off-State Current Perspective", IEEE Access, vol. 13, pp. 199876–199882, Nov. 2025. [ Website ]
[6] M.-W. Kim, H.-J. Park, M.-K. Lee, E.-C. Yun, S.-M. Kang, D.-E. Bang, T.-H. Kil, D. Sohn, and J.-Y. Park*, "Study on the Impact of Deuterium Annealing Duration on MOSFET Performance", Semicond. Sci. Technol., vol. 40, no. 11, p. 115017, Nov. 2025. [ Website ]
[5] S.-J. Jeon, H.-J. Park, S.-J. Chang, M.-K. Lee, E.-C. Yun, T.-H. Kil, J.-W. Yeon, M.-W. Kim, and J.-Y. Park*, "First Demonstration of Rapid Deuterium Annealing for Interface Trap Reduction in HKMG MOSFETs", Semicond. Sci. Technol., vol. 40, no. 8, p. 08LT01, Aug. 2025. [ Website ]
[4] M.-K. Lee, H.-J. Park, T.-H. Kil, J.-W. Yeon, E.-C. Yun, M.-W. Kim, and J.-Y. Park*, "W-Shaped Silicon Channels to Increase the Channel Perimeter and Improve the Output Current of Multi-Bridge-Channel FETs", Silicon, vol.17, pp. 817–823, Feb. 2025. [ Website ]
[3] J.-W. Yeon, H.-J. Park, E.-C. Yun, M.-K. Lee, T.-H. Kil, Y.-S. Kim*, and J.-Y. Park*, "Improvement of Surface Roughness in SiO2 Thin Films via Deuterium Annealing at 300 °C", IEEE Trans. Nanotechnol., vol. 24, pp. 54–58, Jan. 2025. [ Website ]
[2] T.-H. Kil, J.-W. Yeon, H.-J. Park, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-M. Kang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for HfO2 /SiO2 Gate Dielectric in Silicon MOSFETs", IEEE J. Electron Devices Soc., vol. 12, no. 1, pp. 1030–1033, Dec. 2024. [ Website ]
[1] T.-H. Kil, H.-J. Park, J.-W. Yeon, M.-K. Lee, E.-C. Yun, and J.-Y. Park*, "Durability of Low-Temperature Deuterium Annealing Against Ionizing Radiation in MOSFETs", IEEE Trans. Electron Devices, vol. 71, no. 9, pp. 5177–5181, Sept. 2024. [ Website ]
[4] A-Y. Kim, D.-E. Bang, H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, M.-S. Kim, and J.-Y. Park*, "Study on Hetero Gate Dielectrics to Reduce Ambipolar Current in Nanosheet Tunneling FETs", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 38, no. 3, pp. 296–301, May 2025. [ Website ]
[3] S.-M. Kang, Y.-J. Choi, H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, M.-S. Kim*, and J.-Y. Park*, "Study on Multiple Post-Metallization Annealing for Enhancing the Performance and Reliability of Silicon MOSFETs", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 38, no. 2, pp. 187–192, Mar. 2025. [ Website ]
[2] H.-S. Jee, D. Sohn, J.-W. Yeon, T.-H. Kil, H.-J. Park, E.-C. Yun, M.-K. Lee, and J.-Y. Park*, "Fabrication of Low-Cost Physically Unclonable Function (PUF) Chip using Multiple Process Variables", Trans. Electr. Electron. Mater. [ Website ]
[1] H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, and J.-Y. Park*, "Recovery of Radiation-Induced Damage in MOSFETs using Low-Temperature Heat Treatment", Trans. Electr. Electron. Mater. [ Website ]
[5] 박준영, 손돌, 박효준, 윤의철, "측면 채널을 둘러싸는 매립형 워드 라인 구조를 갖는 DRAM 셀 트랜지스터 및 그 제조 방법", KR 10-2026-0006170, 2026.01.13.
[4] 박준영, 손돌, 김민우, 연주원, 박효준, 이문권, 윤의철, "브이-노치 메탈 접촉 구조를 갖는 나노시트 반도체소자 및 그의 제조방법", KR 10-2025-0080331, 2025.06.18.
[3] 박준영, 윤의철, 김민우, 강상민, "반응기 챔버 및 이를 포함하는 급속 저온 중수소 열처리 시스템", KR 10-2025-0064149, 2025.05.16.
[2] 박준영, 이문권, 연주원, 박효준, 길태현, 윤의철, 김민우, 전수진, "임베디드 게이트 구조를 갖는 나노시트 반도체 소자", KR 10-2891735, 2025.11.24.
[1] 박준영, 이문권, 연주원, 박효준, 길태현, 윤의철, 김민우, 전수진, "임베디드 게이트 구조를 갖는 나노시트 반도체 소자", KR 10-2891735, 2025.11.24.
[15] D. Sohn, S.-M. Kang, D.-E. Bang, E.-C. Yun, M.-K. Lee, H.-J. Park, M.-W. Kim, and J.-Y. Park*, "DRAM Cell Transistor with Wrap-Around Word-Line (WAW) Structure for Enhancing Read/Write Performance", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[14] S.-M. Kang, D.-E. Bang, D. Sohn, H.-J. Park, E.-C. Yun, M.-W. Kim, M.-S. Kim, and J.-Y. Park*, "Multi-Level Cell Physically Unclonable Function (PUF) Based on Dual Physical Parameters in Silicon MOSFETs", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[13] M.-W. Kim, H.-J. Park, E.-C. Yun, S.-M. Kang, D.-E. Bang, D. Sohn, and J.-Y. Park*, "Comparative Study of Multiple High-Pressure Rapid Deuterium Annealing for MOSFET Performance Enhancement", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[12] M.-W. Kim, H.-J. Park, E.-C. Yun, S.-M. Kang, D.-E. Bang, D. Sohn, and J.-Y. Park*, "Study on the Efficiency of Deuterium Annealing for Various Process Durations", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[11] Y.-S. Lee, E.-C. Yun, H.-J. Park, and J.-Y. Park*, "Nanosheet FETs with an Inner Spacer Barrier for Suppression of Substrate Parasitic Effects and Punch-Through", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[10] J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, D.-E. Bang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for Improved Immunity against Hot-Carrier Injection in HKMG MOSFETs", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[9] M.-K. Lee, H.-J. Park, E.-C. Yun, J.-W. Yeon, T.-H. Kil, M.-W. Kim, S.-J. Jeon, D.-E. Bang, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Partial Trench Gate Nanosheet FETs for Enhanced ION/ IOFF Ratio", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[8] D.-E. Bang, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Junction Depth Engineered Trench Gate Nanosheet FETs for Suppressing Leakage Current in Parasitic Substrate Channels", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[7] A-Y. Kim, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, D.-E. Bang, S.-M. Kang, and J.-Y. Park*, "Hetero-Gate Dielectric Structures for Reducing Ambipolar Current in Nanosheet Tunneling FETs", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[6] T.-H. Kil, J.-W. Yeon, H.-J. Park, D.-E. Bang, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Material Engineering of Inner Spacer in Nanosheet FETs to Reduce Off-State Current", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[5] T.-H. Kil, H.-J. Park, J.-W. Yeon, E.-C. Yun, M.-K. Lee, D. Sohn, H.-S. Jee, S.-M. Kang, A-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for Enhanced Ionizing Radiation and Electrical Stress Immunity in MOSFETs", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]
[4] H.-S. Jee, D. Sohn, J.-W. Yeon, H.-J. Park, T.-H. Kil, E.-C. Yun, M.-K. Lee, S.-M. Kang, A-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park*, "Development of Physically Unclonable Function (PUF) using Multiple Process Variables", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]
[3] Y.-J. Choi, S.-M. Kang, H.-J. Park, T.-H. Kil, J.-W. Yeon, H.-S. Jee, E.-C. Yun, M.-K. Lee, D. Sohn, D.-E. Bang, A-Y. Kim, and J.-Y. Park*, "Impact of Hydrogen Passivation after Deuterium Annealing in the Fabrication of Silicon MOSFETs", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]
[2] D.-E. Bang, A-Y. Kim, Y.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, D. Sohn, H.-S. Jee, S.-M. Kang, Y.-J. Choi, and J.-Y. Park*, "Optimization of Doping Profile for Improved Performance of Nanosheet FET", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]
[1] E.-C. Yun, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, H.-S. Jee, D. Sohn, S.-M. Kang, A.-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park*, "Spacer-Less Trench Gate Nanosheet FET for Improved On-State Current and Simplified Fabrication Process", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]
중수소 기반의 반도체 공정기술 및 서비스 개발 (2024.05.01 - 2024.12.31), 과학기술정보통신부
Teaching Assistant for '반도체소자공정실험', Spring, 2024
Teaching Assistant for '종합설계I', Autumn, 2025
Teaching Assistant for '종합설계II', Spring, 2026