Embedded systems are much more specialized than general-purpose computer systems. They are designed to provide specific functions. These specialized functions require several important design considerations. Embedded systems must be low cost and power efficient, and must be designed to be as small as possible while meeting real-time constraints for execution completion. These considerations, along with compiler design and program optimization techniques, create constraints on the system architecture design. These conditions interact with each other and must be balanced (e.g., making the system smaller and faster generally increases cost and power consumption). A typical embedded system consists of a processor core, program memory, and application-specific integrated circuits (ASICs). The cost of developing an integrated circuit is related to the size of the system. The largest portion of an integrated circuit is often used for memory to store the application. Therefore, techniques to reduce the size of code and data are very important in reducing the cost of producing such systems. The relevant techniques for embedded systems are not yet perfect. We live in an era where general-purpose computers have abundant memory and processing speeds that are astonishingly fast. Therefore, issues such as the size constraint of compiled binary code have been given less priority than other optimization techniques. Therefore, compiler techniques for embedded system design that satisfy these constraints are developed to support the following:

1. Compilation techniques for low-cost architectures such as MCUs (microcontroller units), DSPs (digital signal processors), and ASICs (application-specific instruction set processors)

2. Rich intermediate representations (IRs) that support the complex instruction sets above, and efficient register allocation, scheduling, and code selection techniques based on IRs

3. Integrated optimization management techniques that enable easy optimization of various architectures

Embedded systems designed for various purposes are made of various memory structures and diverse instruction sets. Therefore, we need to optimally redesign existing optimization techniques such as code size, register usage, instruction scheduling, and data placement to fit the new hardware design.

To achieve these goals, ESPRESSO Lab. studies software optimization by classifying it into three levels: algorithm level, source code level, and instruction level. In addition, we are conducting research on microarchitecture design co-optimization technology for further system optimization.

LLVM-based compiler development for emerging algorithms like machine learning, deep learning

The compiler acts as a bridge between the machine learning (ML) model and the hardware architecture on which the machine learning model runs. The compiler performs two tasks: transformation and optimization, which are performed at several stages of the intermediate representation (IR). These two tasks are not necessarily separate. Program code/data optimization is performed at all stages from high-level IR to low-level IR. Transformation refers to the compiler task of generating hardware-native code for the ML model so that it can be executed on a specific hardware. Optimization refers to the compiler technique that optimizes the ML model so that it can be executed efficiently on the hardware. There are two ways to optimize the ML model: local and global optimization. Local optimization is when a task or a set of tasks in the ML model is optimized. Global optimization is when the entire computational graph is optimized end-to-end. Our research focus is to develop an optimizing compiler for commercial-grade machine learning frameworks using the LLVM compiler framework.

Data partitioning & allocation algorithm for low power memory sytems in embedded systems

When a program developer writes source code, it is the compiler's job to make it executable on a computing device. The compiler, which performs this conversion process, generates a set of instructions and data in binary format. At this time, the order of data arrangement, the selection of instruction sets, and the location of program code blocks are determined by the compiler technology. The problem here is that the optimal instruction selection and data arrangement for various memory architectures and instruction architectures are dependent on the compiler. This is because the system performance can vary significantly depending on these decision parameters. To solve this problem, we are researching the development of universal data optimization and instruction selection technologies for various instruction architectures and various memory architectures. These optimization technologies maximize the utilization of upper memory in various memory hierarchies to improve the overall system performance and optimize the energy consumption of the program.

Code scheduling & mapping algorithm for accelerator architectures such as GPU, reconfigurable array architecture, and application specific integrated circuit

The focus of the code scheduling/mapping algorithm research is to develop integrated code mapping and scheduling management technologies for various computing architectures. To make this possible, we need to define and write an architecture description file that describes the characteristics of the computing architecture, and develop a meta-algorithm layer that applies the optimal code mapping and scheduling techniques that fit this description file. The focus of this study is the development of an integrated program code mapping/scheduling management technology for various types of embedded system architectures.