Embedded Files
Lecture-Lab-Study: 2-1-3
Lecture-Lab-Study: 2-1-3
Credits: 3
Credits: 3
Meeting Time: Tuesday and Thursday 12:30 PM to 1:45 PM
Meeting Time: Tuesday and Thursday 12:30 PM to 1:45 PM
Former Instructor: Dr. Kevin Lu, Teaching Professor and Associate Chair for Undergraduate Studies, Electrical and Computer Engineering (ECE)
Former Instructor: Dr. Kevin Lu, Teaching Professor and Associate Chair for Undergraduate Studies, Electrical and Computer Engineering (ECE)
$ git clone https://github.com/kevinwlu/dsd.git
Office Hours: Tuesday and Thursday 12:00 PM to 2:30 PM
Office Hours: Tuesday and Thursday 12:00 PM to 2:30 PM
Prerequisite: ENGR 245 Circuits and Systems
Prerequisite: ENGR 245 Circuits and Systems
Corequisite: None
Corequisite: None
Cross-listed with: None
Cross-listed with: None
2022 Spring Schedule
2022 Spring Schedule
2022-01-18 Syllabus
2022-01-20 Chapters 1-3
2022-01-25 Chapters 4-6, Download and install GHDL and GTKWave
2022-01-27 Chapters 7-8, One-hot coding, Gray code, GHDL examples: hello and half adder
2022-02-01 Chapters 9-10, GHDL example: full adder
2022-02-03 Chapters 11-13, GHDL examples: D flip-flop and T flip-flop
2022-02-08 Appendices A to C, GHDL examples: 4-to-1 multiplexer and 1-to-4 demultiplexer
2022-02-10 Semiconductor device fabrication and electronic design automation (EDA)
2022-02-15 Download and install Vivado (Standard Edition) and cable drivers
2022-02-17 FPGA Lab 1 Project 1
2022-02-22 No Class (Monday Class Schedule)
2022-02-24 FPGA Lab 1 Project 2
2022-03-01 FPGA Lab 2
2022-03-03 FPGA Lab 2
2022-03-08 FPGA Lab 3
2022-03-10 FPGA Lab 3
2022-03-15 No Class (Spring Recess)
2022-03-17 No Class (Spring Recess)
2022-03-22 FPGA Lab 6
2022-03-24 FPGA Lab 6
2022-03-29 FPGA Lab 4
2022-03-31 FPGA Lab 4
2022-04-05 FPGA Lab 5
2022-04-07 FPGA Lab 5
2022-04-12 FPGA Project
2022-04-14 FPGA Project
2022-04-19 FPGA Project
2022-04-21 FPGA Project
2022-04-26 FPGA Project
2022-04-28 FPGA Project
2022-05-03 FPGA Project
2022-05-10 Final Exam Schedule 8:00-11:00
2021 Fall Schedule
2021 Fall Schedule
2021-08-31 Syllabus
2021-09-02 Chapters 1-3
2021-09-07 Chapters 4-6, Download and install GHDL and GTKWave
2021-09-09 Chapters 7-8, one-hot coding, Gray code, GHDL examples: hello and half adder
2021-09-14 Chapters 9-10, GHDL example: full adder
2021-09-16 Chapters 11-13, GHDL examples: D flip-flop and T flip-flop
2021-09-21 Appendices A to C, GHDL examples: 4-to-1 multiplexer and 1-to-4 demultiplexer
2021-09-23 Semiconductor device fabrication and electronic design automation (EDA)
2021-09-28 Download and install Vivado (Standard Edition) and cable drivers
2021-09-30 FPGA Lab 1 Project 1
2021-10-05 FPGA Lab 1 Project 2
2021-10-07 FPGA Lab 2
2021-10-12 No Class (Monday Class Schedule)
2021-10-14 FPGA Lab 3
2021-10-19 FPGA Lab 4
2021-10-21 FPGA Lab 5
2021-10-26 FPGA Lab 6
2021-10-28 FPGA Project
2021-11-02 FPGA Project
2021-11-04 FPGA Project
2021-11-09 FPGA Project
2021-11-11 FPGA Project
2021-11-16 FPGA Project
2021-11-18 FPGA Project
2021-11-23 FPGA Project
2021-11-25 No Class (Thanksgiving)
2021-11-30 FPGA Project
2021-12-02 FPGA Project
2021-12-07 FPGA Project
2021-12-09 FPGA Project
2021-12-13 Final scheduled at 8:00 AM - 11:00 AM
Course Learning Outcomes (CLOs)
Course Learning Outcomes (CLOs)
Program Outcome 1: (Complex Problem Solving)
1.2 The student will be able to efficiently model a complex digital system as a hierarchy of interconnected components, taking advantage of regularity and component reuse.
2.1 The student will be able to apply VHDL entity/architecture modeling to represent component inputs and outputs and also internal signals, variables, and operations.
2.3 The student will be able to develop VHDL models of systems using behavioral, structural, and dataflow concepts to describe the internal behavior and/or structure of the design.
Program Outcome 2: (Design)
2.2 The student will be able to build VHDL models of complex digital circuits suitable for synthesis where the target platform is an FPGA or ASIC logic library. Spring 2023 Addendum: The student will be encouraged to extend commercial FPGA evaluation boards with other ASIC (Application Specific Integrated Circuits) digital and analog chips.
2.4 The student will be able to use VHDL to design complex synthesizable finite-state machines using Mealy and/or Moore architectures.
2.5 The student will be able to write test vectors for a digital system and develop a VHDL test-bench to apply these vectors using file based input/output operations.
Program Outcome 3: (Communication)
1.1 The student will be able to develop technical documentation of a complex digital system using hardware description language and schematic representations and to evaluate the correct function and performance based on simulations of the system.
Program Outcome 6: (Experimentation)
1.3 The student will be able to represent and document designs, perform simulations, and synthesize implementations using software tools provided by an FPGA vendor.
Lectures 0-14, Homework 1-7, Labs 1-6, and Projects I-II
Lectures 0-14, Homework 1-7, Labs 1-6, and Projects I-II
Digilent Nexys 2 Spartan-3E field-programmable gate arrays (FPGAs) Trainer Board, Reference Manual
Digilent Pmod Modules including KYPD (16-button keypad) and an optional 2x6 Pin Pmod cable, I2S (Inter-IC Sound), and AD1 (two channel, 12-bit analog-to-digital converter) and a 5 kΩ potentiometer
Xilinx ISE (Integrated Synthesis Environment), ISE Design Suite, ISE WebPACK Design Software
Updates
Updates
Textbook (PDF): Free Range VHDL by Bryan Mealy and Fabrizio Tappero
Table of Contents
Acknowledgments
Purpose of This Book
Introduction to VHDL
VHDL Invariants
VHDL Design Units
VHDL Programming Paradigm
Standard Models in VHDL Architectures
VHDL Operators
Using VHDL for Sequential Circuits
Finite State Machine Design Using VHDL
Structural Modeling in VHDL
Registers and Register Transfer Level
Data Objects
Looping Constructs
Standard Digital Circuits in VHDL
Appendix A. VHDL Reserved Words
Appendix B. Standards VHDL Packages: 1) IEEE Standard Libraries, 2) Non-standard Libraries
Appendix C. VHDL Reference Cards
Appendix D. Contributors to This Book
Free Range Factory IP Cores
VHDL GitHub Repositories
VHDL Tutorials
Basic VHDL Tutorials by VHDLwhiz
VHDL Tutorial: Learn by Example by Weijun Zhang, UC Riverside, July 2001
VHDL Tutorial by Jan Van der Spiegel, University of Pennsylvania
NI Digilent Nexys 4 DDR (double data rate) rebranded as Nexys A7-100T ($261.75), Reference Manual, Out of Box Demo
Other Xilinx FPGAs: Digilent Cmod A7-35T ($84.15), Basys 3 ($123.75), Digilent ZedBoard ($529.98), Xilinx ZCU102 ($2,994)
Configurable logic block (CLB)
JTAG (Joint Test Action Group), OpenOCD (Open On-Chip Debugger)
SPI (Serial Peripheral Interface) and QSPI (Quad-SPI)
Digital signal processor (DSP)
Pulse-width modulation (PWM) audio output, pulse-density modulation (PDM) microphone
Digilent Peripheral Modules (Pmods)
KYPD (16-button keypad) and and an optional 2x6 Pin Pmod cable
I2S2 (Inter-IC Sound) and a speaker
AD1 (two channel, 12-bit analog-to-digital converter) and a 5 kΩ potentiometer
Design software: Xilinx Vivado
Download Xilinx Unified Installer, i.e., Windows or Linux Web Self Extracting Installer
Select 1) Vivado, 2) Devices: 7 Series Devices, and 3) Installation Options: Install Cable Drivers
Optional: Add-On for MATLAB and Simulink (Model Composer and System Generator)
Vidado Design Suite User Guide: Release Notes, Installation, and Licensing
FPGA Labs: Create a Google Site and GitHub repository, and install Xilinx Vivado on a Windows or Linux laptop computer
Lab 1: Seven-Segment Decoder
Lab 2: Four-Digit Hex Counter
Lab 3: Bouncing Ball (VGA display or VGA to HDMI cable)
Lab 4: Hex Calculator (Pmod KYPD and a 2x6 Pin Pmod cable)
Lab 5: Digital-to-Analog Converter (DAC) Siren (Pmod I2S and a peaker or headphone)
Lab 6: Video Game PONG (Pmod AD1, a 5 kΩ potentiometer and VGA display)
Intel FPGAs: Terasic DE0-CV ($140), User Manual, CD ROM
J. Hamblen, T. Hall, and M. Furman, Rapid Prototyping of Digital Systems, SoPC (System-on-a-Programmable Chip) Edition (PDF), 2007
TinyFPGA: BX ($38), User Guide, GitHub repository
First project tutorial (apio_template) in Verilog (top.v) with the on-board user LED blinking “SOS” in Morse code
APIO IDE
Lattice iCE FPGA
Lattice ECP5 FPGA
Lattice CrossLink-NX FPGA
Semiconductor Device Fabrication
Semiconductor Device Fabrication
Three-dimensional integrated circuit (3D IC), through-silicon via (TSV)
WikiChip, chiplet, multi-chip module (MCM)
The International Technology Roadmap for Semiconductors (ITRS)
The International Roadmap for Devices and Systems (IRDS)
Samuel K. Moore, "A Better Way to Measure Progress in Semiconductors," July 21, 2020
Samuel K. Moore, "The Node is Nonsense," IEEE Spectrum, Vol. 57, No. 8, Aug. 2020, pp. 24-30
Die shrink provides more chips onto each wafer, resulting in lowered manufacturing costs per chip
Multigate device, field-effect transistor (FET), fin FET (FinFET), gate-all-around FET (GAAFET)
Application-specific integrated circuit (ASIC), FPGA -to-ASIC conversion
List of semiconductor device fabrication steps
Yield is the fraction of dies on the yielding wafers that perform properly
List of semiconductor materials
List of silicon producers including high-purity silicon and silicon wafer manufacturers
Silicon wafer producers: Shin-Etsu Chemical, SUMCO, GlobalWafers, Siltronic
Pure play foundries: TSMC, GlobalFoundries, UMC, SMIC, Tower Semiconductor (aquired by Intel), Innovations for High Performance Microelectronics (IHP)
Equipment suppliers
Semiconductor industry, list of semiconductor companies, integrated device manufacturer (IDM), original design manufacturer (ODM)
US: Allied Electronics and Automation, Amazon, AMD, Analog Devices, Apple, Atmel (acquired by Microchip), Broadcom, Cirrus Logic, Cisco Silicon One, Cree, Cypress (acquired by Infineon), Diodes Incorporated, Facebook, Google, IBM, Intel, Lattice, Marvell, Maxim Integrated (acquired by Analog Devices), Microchip, Micron, Microsemi (acquired by Microchip), Microsoft, Nvidia, ON Semiconductor, Qorvo, Qualcomm, Qualcomm Atheros, Rambus, Silicon Labs, SkyWater, Skyworks, Tesla, TI, Xilinx (AMD announced its acquisition of Xilinx in October 2020), Western Digital
Europe: ams AG, ARM, Dialog Semiconductor (acquired by Renesas), FTDI, Melexis, Nexperia, Nordic Semiconductor, NXP, Infineon, RS Components, STMicroelectronics, u-blox
China: Alibaba, Baidu, BBK (including Oppo Digital, Vivo), Bitmain, Canaan Creative, Haier, HiSilicon, Huawei, Innosilicon, Lenovo, Meizu, Tencent, Unisoc, Xiaomi, ZTE
Taiwan: Acer, Asus, BenQ, Compal, Foxconn, Inventec, MediaTek, Nanya, Pegatron, Powerchip, Quanta, Ralink, Realtek, Wistron
Japan: Fujitsu, Hitachi, Kioxia, Murata, NEC, Panasonic, Renesas, Sony, Toshiba
South Korea: LG, Samsung Electronics, SK Hynix
List of products
Cerebras Wafer-Scale Engine (WSE)
Hisilicon Ascend 910
Huawei Ascend 910 AI processor
Qualcomm Snapdragon, list of Qualcomm Snapdragon systems-on-chip
Samsung Exynos
Tesla Dojo, A Guide to Tesla’s Configurable Floating Point Formats and Arithmetic (PDF)
Mixed-signal integrated circuits have both analog electronics and digital electronics on a single semiconductor die
Scriptable multi-threaded sysbench benchmark tool
EDA companies
Synopsys (Synplify Pro, Synplify Premier, Identify RTL Debugger)
Cadence Design Systems (Virtuoso Layout Suite, Innovus Implementation System )
Siemens EDA, formerly Mentor Graphics (ModelSim PE Student Edition)
Process design kit (PDK)
GDSII graphic design system database file format
Design rule checking (DRC)
Layout versus schematic (LVS)
High-frequency structure simulator (HFSS)
Simulation Program with Integrated Circuit Emphasis (SPICE)
Library exchange format (LEF)
EDA Playground with EPWave
gEDA project
Open-source simulators
Tutorial at FOSDEM 2018
The "hello, world" program
Value change dump (VCD)
Open-Source EDA: KiCad, SmartSim (for Windows and Linux PCs and the Raspberry Pi) developed by Ashley Newson in 2011 when he was 16
Schematic Editor: CircuitLab
MATLAB HDL Coder
Doxygen usage for documenting VHDL code with comment blocks starting with "--!" and OPTIMIZE_OUTPUT_VHDL = YES in the Doxygen configuration file
Textbook References
Textbook References
Chapter 1: Introduction to VHDL
Chapter 1: Introduction to VHDL
Chapter 2: VHDL Invariants
Chapter 2: VHDL Invariants
Chapter 3: VHDL Design Units
Chapter 3: VHDL Design Units
Declaration of the std_logic enumerated type (see Listing 11.2, Chapter 11, Page 152 or IEEE 1164)
Bit numbering refers to the bit position in a binary number
The least significant bit (LSB) in a binary integer determines whether the number is even or odd
The most significant bit (MSB) in a binary integer has the greatest value
Endianness refers to the order of bytes within a binary representation of a number in computing
The prefix 0x denotes hexadecimal numerals, e.g., 0x2AF3 = 10 995
Refer to Section 11.9 (Page 150) for signed and unsigned types
SIGNED types represent signed numerical values, which can be positive, zero, or negative
The Compiler interprets each SIGNED type as a two's complement binary representation; the leftmost bit indicates whether the value is positive or negative
UNSIGNED types represent unsigned numerical values, which can be positive or zero only
The Compiler interprets each UNSIGNED type as a binary number, with the digit on the left as the MSB
Chapter 4: VHDL Programming Paradigm
Chapter 4: VHDL Programming Paradigm
George Boole 1815-1864, Boolean algebra, std_logic types
Maurice Karnaugh, Karnaugh map, lookup table (LUT)
Chapter 5: Standard Models in VHDL Architectures
Chapter 5: Standard Models in VHDL Architectures
Chapter 6: VHDL Operators
Chapter 6: VHDL Operators
M mod N = ( M rem N + N ) rem N
Chapter 7: Using VHDL for Sequential Circuits
Chapter 7: Using VHDL for Sequential Circuits
Flip-flops, D (data) flip-flop, T (toggle) flip-flop
Rising edge-triggered (RET), falling edge-triggered (FET)
VHDL predefined attributes, e.g., CLK'event: the attribute "event" of the signal CLK followed by an apostrophe
Chapter 8: Finite State Machine Design Using VHDL
Chapter 8: Finite State Machine Design Using VHDL
Finite-state machine (FSM), e.g., turnstiles, traffic lights, vending machines, elevators, combination locks
Mealy vs. Moore machine overview video by Bruce Boatner
Edward Moore 1925-2003, Moore machine (1956) with output values determined by its current state
Have outputs defined inside their state bubbles
Transition conditions listed on their transition arrows
May seem a bit more intuitive in their notation
May require more states than a Mealy machine
George Mealy 1927-2010, Mealy machine (1955) with output values determined by its current state and the current inputs
Input and output variables listed on transition arrows
May seem a bit more abstract in their notation
Can be more efficient and flexible than Moore machine
May require less hardware to implement
One-hot is a group of bits with a single high (1) bit and all the others low (0)
One-cold is a group of bits with all bits are '1' except one '0'
Chapter 9: Structural Modeling in VHDL
Chapter 9: Structural Modeling in VHDL
Chapter 10: Registers and Register Transfer Level
Chapter 10: Registers and Register Transfer Level
Chapter 11: Data Objects
Chapter 11: Data Objects
Complex programmable logic device (CPLD)
Clock divider (frequency divider), e.g., 50 MHz to 1 kHz clock divider (VHDL code)
Digital clock manager (DCM), mixed-mode clock manager (MMCM), phase-locked loop (PLL)
Chapter 12: Looping Constructs
Chapter 12: Looping Constructs
Chapter 13: Standard Digital Circuits in VHDL
Chapter 13: Standard Digital Circuits in VHDL
Counter, shift register, digital comparator, binary-coded decimal (BCD), seven-segment display, multiplexer, decoder
Appendix
Appendix
Standards
Standards
The IEEE Council on Electronic Design Automation (CEDA)
The IEEE Computer Society Design Automation Standards Committee (DASC)
IEEE 1076 IEEE Standard VHDL Language Reference Manual
IEEE 1076.1 IEEE Standard VHDL Analog and Mixed-Signal Extensions
IEEE 1164 IEEE Standard Multivalue Logic System for VHDL Model Interoperability
IEEE 1149.1 IEEE Standard for Test Access Port and Boundary-Scan Architecture
IEEE 1364 IEEE Standard for Verilog Hardware Description Language
IEEE 1800 IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
Open Computing Language (OpenCL)
OSHWA (Open Source Hardware Association)
SYZYGY open standard for high-performance peripheral connectivity
ButterStick (with a Lattice ECP5 FPGA) created by Greg Davill
Xilinx References
Xilinx References
Xilinx Design Hubs
Xilinx Vivado Design Suite User Guide: Using Constraints, UG903 (v2018.2), June 6, 2018
Vivado Design Suite Tutorial: Using Constraints, UG945 (v2018.3), December 5, 2018
Xilinx Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator, UG994 (v2018.3), December 5, 2018
Xilinx Vivado Design Suite Tool Command Language (Tcl) Command Reference Guide, UG835 (v2017.4), February 2, 2018
Xilinx Constraints Guide, UG625 (v. 14.5), April 1, 2013
User Constraints File (UCF) are replaced with Xilinx Design Constraints (XDC)
Xilinx Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit (Passive)
Xilinx SDAccel development environment
Versal Adaptive Compute Acceleration Platform (ACAP), WP505 (v1.0), October 2, 2018
Xilinx PYNQ uses the Python language and libraries with Zynq, Zynq UltraScale+, Zynq RFSoC, Alveo accelerator boards, and AWS F1
MyHDL Python-based HDL
Verilog and SystemVerilog References
Verilog and SystemVerilog References
Verilog HDL Quick Reference Card (PDF)
SystemVerilog Reference Guide by Aldec
Verilog HDL Quick Reference Guide (PDF) by Stuart Sutherland
Verilog HDL Quick Reference (PDF) by Rajeev Madhavan
Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition (PDF) by Samir Palnitkar
Digital Design with an Introduction to the Verilog HDL (PDF) by M. Morris Mano and Michael D. Ciletti
FPGA Prototyping by Verilog Examples, Xilinx Spartan-3 Version (PDF) by Pong P. Chu
Verilog HDL Synthesis: A Practical Primer (PDF) by Jayaram Bhasker
LinkedIn Learning (formerly Lynda) course "Learning FPGA Development" by Eduardo Corpeño (1h 9m)
ChipVerify Tutorials on Verilog, SystemVerilog, and Universal Verification Methodology (UVM)
FPGA Projects
FPGA Projects
Quantum Computing
Quantum Computing
Stevens Center for Quantum Science and Engineering (CQSE)
Quantum finite automaton (QFA)
Quantum processing units (QPUs)
Create an IBM Quantum account
IBM Quantum Lab Qiskit Tutorials include a core reference set of notebooks outlining the features of Qiskit
Games
Games
Further Reading
Further Reading
Parallel Programming for FPGAs by Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer, Kastner Research Group (KRG), UC San Diego
John von Neumann 1903-1957, Von Neumann Architecture
Alan Turing 1912-1954, Turing Machine
John Tukey 1915-2000, bit
Werner Buchholz 1922-2019, byte
David Benson, nibble
Richard Hamming 1915-1998, coding theory
Claude Shannon 1916-2001, information theory
Richard Feynman 1918-1988, The Feynman technique
Chuck Peddle 1937-2019, MOS Technology 6502
GRASS: GRAph Spectral Sparsifier
Run customizable FPGAs in the Amazon Elastic Compute Cloud (EC2) F1 instances
List of bitcoin mining ASICs
Google Pixel Titan M chip, Meltdown security vulnerability, Meltdown and Spectre, Row hammer
SSD (solid-state drive), U.2, SATA (serial AT attachment), M.2, NVMe (non-volatile memory express)
Google Sites
Report abuse