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Text Books
VLSI Synthesis of DSP Kernels: algorithmic and architectural transformations / Mahesh Mehendale (2001)
VLSI Digital signal processing systems: design and implementation / Keshab K. Parhi (2010)
FPGA-based Implementation of Signal Processing Systems / Roger Woods …[et al]. (2008)
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Lecture Slides
Lecture Slides
My lecture slides.
*These lecture slides are from K.K.Parhi.
Assignments
Assignments
IMPORTANT !!
Only those assignments will be evaluated which are submitted personally .
Assignment 1 (Last date of submission February 1, 2011)
1. Compare BD, SFG, DFG and DG using one 5-tap FIR filter.
Assignment 2 (Last date of submission February 16, 2011)
A DFG is shown below. Time required for each operation is T
• What is the maximum achievable sample rate in this system?
• Place pipeline registers at appropriate feed-forward cutsets such that the sample rate of this system can be approximately equal to 1/T. Clearly identify the feed forward cutsets and count the total number of pipelining registers required.
Assignment 3 (Last date of submission March 31, 2011)
Design a systolic array for 8-tap FIR filter.
Assignment 4 (Last date of submission March 14, 2011)
Show that removing ‘k’ from the algorithm of Floyd Warshall algorithm does not affect the correctness of the algorithm.
Assignment 5 (Last date of submission March 30, 2011)
Apply clock minimization algorithm on the graph shown. Show all the steps.
Class Schedule
Class Schedule
Lecture Schedule
MONDAY CR5 10:00-11:00
FRIDAY LT2 10:00-11:00
SATURDAY CR1 09:00-10:00
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