ACADEMIC BACKGROUND:

• Ph.D. (Microelectronics), June 2011: Indian Institute of Technoloy, Powai, Mumbai.

       Area of Specialization: VLSI & Microelectronics

       Title of Thesis: Variability Aware Performance Evaluation of Nanoscale CMOS Devices and Circuits

• M.Tech(Microelectronics), January 2000:Indian Institute of Technology, Powai, Mumbai.

      Area of Specialization: VLSI & Microelectronics

      Title of Thesis: Lateral Asymmetric Channel (LAC) MOSFETs for ULSI Applications

• B.E.(Electronics), August 1992: Dr. Babasaheb Ambedkar Marathwada University, Aurangabad. 

RESEARCH INTEREST:

• Statistical Design of Nanoscale Integrated Circuits

• Low Power VLSI Design

• VLSI Signal Processing

• FPGA based Embedded System Design

EXPERIENCE IN ACADEMIC LEADING:

• Member of Board of Studies of Electronics and Telecommunication Engineering in University of Mumbai from November 2013 to November 2015.

• Chairman of Board of Studies of Electronics Engineering in University of Mumbai from April 2016 to till date.

• Chairman of Institute of Electronics and Telecommunication Engineering (IETE), Navi Mumbai Centre from July 2016 to June 2018.

• Management Representative for ISO Certification 9001:2000 in MGM’s College of Engineering and Technology, Kamothe, Navi Mumbai.

• Head of Department of Electronics and Telecommunication Engineering in Don Bosco

• Institute of Technology, Kurla(W), Mumbai from July 2014 to June 2018.

• Publication Chair for International Conference on Technologies for Sustainable, Development 2015.

• Publication Chair and Co-convener for IETE International Conference on Recent Trends on Sustainable Technologies, July 2018

• IEEE Student Branch Counseller from January 2000 to December 2002.

• IQAC coordinator since July 2018 to till date.

• Dean Administration since November 1, 2021 to till date.
  
  

WORK EXPERIENCE:

• Currenty working as Professor in Department of Electronics & Telecommunication Engineering at Don Bosco Institute of Technology from July 01, 2015 to till date.

• Associate Professor in Department of Electronics & Telecommunication Engineering in Don Bosco Institute of Technology since July 1, 2011 to June 30, 2015.

• Assistant Professor in Department of Electronics & Telecommunication Engineering in Don Bosco Institute of Technology since July 1, 2004 to June 30, 2011.

• Assistant Professor in Department of Electronics & Telecommunication Engineering in MGM’s College of Engineering and Technology, Kamothe, Navi Mumbai since 1st September 2002 to 30 June 2004.

• Lecturer in Department of Electronics and Telecommunication in MGM’s College of Engineering and Technology, Kamothe, Navi Mumbai since September 9, 1992 to August 31, 2002.

ADDITIONAL RESPONSIBILITIES:

• Member of Academic Advisory Board for Electronics & Telecommunication Engineering in Rajiv Gandhi Institute of Technology, Andheri, Mumbai.

• Panel member for the evaluation of PhD and M.Tech thesis in Gujarat Technological University, Ahemdabad, Gujrat.

• Member of Department Advisory Board for Electronics and Telecommunication Engineering in Terna Engineering College, Nerul, Navi Mumbai.

• Member of Department Advisory Board for Electronics Engineering in Atharva College of Engineering, Malad, Mumbai.

• Research Mentor for faculty and students in Electronics & Telecommunication Engineering in Don Bosco Institute of Technology, Kurla (W), Mumbai.

PROFESSIONAL MEMBERSHIP & RECOGNITION:

• Life Member, Indian Society for Technical Education (LMISTE), New Delhi

• Fellow, Institution of Electronics and Telecommunication Engineer (FIETE), New Delhi

• Recognition as Post Graduate Teacher of University of Mumbai.

• Recognition as Ph.D. guide of University of Mumbai in Electronics & Telecommunication Engineering.

JOURNAL PUBLICATIONS:

1. Sudhakar Mande, A.N.Chandorkar, Cheng Hsaio, Kasa Huang, Y.M.Sheu and Sally Liu, “A Novel Approach to Link Process parameters to BSIM model Parameters,” IEEE Transactions on Semiconductor Manufacturing, vol. 22, no. 4, pp. 544-551, Nov. 2009.

2. Sudhakar Mande, A. N. Chandorkar, Sourabh Chandorkar, “ Process Variation Aware dual-Vth Approach for Low Power Design of Nanoscale CMOS Circuits,” publication in Elseviers Journal of Microelectronics Reliability, August 2011.

3. Mahesh Kadam, Kishor Sawarkar, and Sudhakar Mande, “Comparative analysis and efficient VLSI implementation of FIR filter” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 3, Issue-7, July 2015.

4. Harshada Khandagale, Daniya Quadros, Sudhakar Mande, "Study of Impact of Solar Cell Mismatch of the Performance of PV Module Using PSpice", Journal of Applied Science and Computation ISSN No. 1076-5131, Vol.5, Issue No. 10, October 2018, P-819-824.

5. Laksmi V, M. Iqbal, Kawljeet, Sudhakar Mande, “ Variability Aware Performance Evaluation of CMOS 1-Bit Adder Circuits”, Journal of Applied Science and Computation ISSN No. 1076-5131, Vol.5, Issue No. 10, October 2018, P-825-828.

6. Dattatray Bade and Sudhakar Mande, " Review of USB Bandpass Filter With Multiple Notches for Broadband Applications," Journal of Applied Science and Computation ISSN No. 1076-5131, Vol.5, Issue No. 10, October 2018, P-860-864.

7. Vanitha Soman and Sudhakar S Mande, "Design of a sampler circuit for Flash ADC using 45nm Technology,"  International Journal of Engineering and Advanced technology, Vol.2, Issue-3, Dec-2019.

8. Vanitha Soman and Sudhakar S Mande, "A 4-bit 1GS/s folding Flash ADC suing 45nm Technology," Microprocessor and Microsystems, Elsevier, November 2020.

9. Vanitha Soman and Sudhakar S Mande,  "A 4-bit 4GS/s Differential Current Steering DAC for 16 bit transmitter using 45nm CMOS Technology,"  Applied Nanoscience, Springer, September, 2021. https://link.springer.com/article/10.1007/s13204-021-02101-1 

10. Vanitha Soman and Sudhakar S Mande, " Design of a two-stage folded cascode amplier using SCL 180nm CMOS Technology," Lecturer Notes in Electrical Engineering, Springer, 2020.

11. Vipinkumar R. Pawar, Sudhakar Mande  and Imdad Rizvi (2021) , "Terrain Aware Cellular Network Blind Spot Recovery Algorithm Using AeriaBTS, " IETE Journal of Research, DOI: 10.1080/03772063.2021.1941333

12. Vipinkumar Rajendra Pawar, Sudhakar S. Mande and Imdad Rizvi (2020), "Airborne UAV Remote Sensor Position Accuracy Algorithm in Catastrophes Zones 2020,"  Journal of Aerospace Science and Technology, Volume 72, Issue 1089

CONFERENCE PUBLICATIONS:

1. Sudhakar Mande and A.N.Chandorkar , “Response Surface Methodology for statistical characterization of nanoscale CMOS devices and Circuits,” in Proceedings of International Workshop on Physics of Semiconductor Devices, Dec 2007, pp.297-300.

2. A.N.Chandorkar, Sudhakar Mande and Hiroshi Iwai,“Estimation of Process Variation impact on DG-FinFET using Plackett-Burman Design Experiemt method,” in Proceedings of International Conference on Solid-State and Integrated-Circuit Technology, Oct 2008, pp. 215-218.

3. A.M.Chopade, R.A.Takker, Sudhakar Mande, M.B.Patil and A.N.Chandorkar, “Verification of Parameter Extraction Strategy for MOS Model 11,” in Proceedings of International Conference on Trends in Intelligent Electronic Systems, (TIES 2007) Sathyabama University, Jeppiaar Nagar, Chennai, India.

4. T. Sing,J.Chacko,N.Sebastian, R. Thoppilan, A.Kotrashetti, S.Mande, “Design and optimization of microstrip Hairpin-Line bandpass filter using DOE methodology,” International Conference on Communication, Information & Computing Technology (ICCICT), 2012.

5. Sudhakar Mande, A.N.Chandorka and Hiroshi Iwai, “Computationally Efficient Methodology for Statistical Characterization of Inter- and Intra-die Process variations,” Asia Symposium on Quality Electronic Design, Dec 2013, pp.287-294.

6. Hansel Dsilva, Julian Pinto, Arzhan Elchidana and Sudhakar Mande, “Variability aware performance evaluation of low power SRAM cell”, Asia Symposium on Quality Electronic Design, Dec 2013, pp.183-187.

7. Mahesh Kadam, Kishor Sawarkar, and Sudhakar Mande, “Investigation of Suitable DSP Architecture for Efficient FPGA Implementation of FIR Filter”, International Conference on Communication, Information and Computing Technology, 2015, Pages:1-4.

8. Sayli S. Aphale, Kasusar Fakir, Sushama Kodagali, Sudhakar Mande, “Analysis of various adder circuits in deep submicron process”, International Conference on Automatic Control and Dynamic Optimization Techniques, September 2016.

9. Mohd Iqbal and Sudhakar Mande, “A novel approach in sar-adc for variable conversion time using window detector”, International Conference on Advances in Computing, Communications and Informatics, 2017.

10.  Swati Keni, Sudhakar Mande, "Design and Implementation of Hardware Firewall using FPGA", IEEE I2CT 2018, Pune.

11. Swati Keni, Sudhakar Mande, "Packet Filtering for IPV4 Protocol using FPGA" in International Conference on Intelligent Computing and Control Systems 2018. 

12. Naru Jai, Balaji Dontha, Amiya Tripathy, Sudhakar Mande, "Near Real Time – Sensing System for Hydroponics based Urban farming",IEEE I2CT 2018, Pune. 

13. Vanitha Soman and Sudhakar S Mande,  "Analysis and Design of two stage CMOS OTA using 0.13 m Technology", International Conference on Computer Communication and Power Systems (ICCCPS-2020, March 2020, Sri Venkateswaraa college of technology, Sriperumbudur Tamil Nadu.

14. Vanitha Soman and Sudhakar S Mande, "Design of a two-stage folded cascode amplier using SCL 180nm CMOS Technology," (International Conference on communication, computing and electronics systems(ICCCES 2019)(Scopus indexed Springer) Nov-2019,pp33-38. PPG institute of technology, Coimbatore, Tamil Nadu.)

15. VipinKumar Rajendra Pawar, Sudhakar S. Mande (2021),Ballistics Algorithm For Airborne Remote Sensor Position In Catastrophe Zones,Presentation date 4th April 2021, 2nd International Conference on Unmanned Aerial Systems in Geomatics - 2021 Volume 2

16. Vipinkumar R. Pawar, Sudhakar Mande & Imdad Rizvi (2017), WSN Based Natural Disaster Alert and Analysis, 38th Asian Conference in Remote Sensing (ACRS 2017), June 2017, New Delhi, Hosted By ISRO.

17. Ahmed Ansari, Khan Rizwan, Mohammed Fawzaan Roghay, Shaikh Faisal, Sudhakar Mande, “A Novel Encoder Architecture for 8-bit Flash ADC”, 2021 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON), DOI:10.1109/SMARTGENCON51891.2021.9645882

18. Siddhi Warang, Mark Gracious, Siddhi More, Mangeshi Patil, Sudhakar S. Mande, “Design of Ultra Low Noise High Precision Bandgap Voltage Reference”, 2021 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON), DOI: 10.1109/SMARTGENCON51891.2021.9645889 

19. Dattaray S. Bade; Sudhakar. S. Mande,"Switchable Single/dual Notch Band Electromagnetic Band Gap Structure,"2021 International Conference on Communication information and Computing Technology (ICCICT) DOI: 10.1109/ICCICT50803.2021.9510068

INVITED TALKS:

1. MOSFET Basics and Scaling, STTP, Terna Engineering College, July 2007Nerul, Navi Mumbai.

2. VLSI Design using WinSPICE, Nov 2008, STTP, Don Bosco Institute of Technology, Kurla, Mumbai.

3. Electronic Circuit Simulation using SPICE, STTP, KC College of Engineering, Thane, Jan 2009.

4. Modern Electronic Design Techniques using WinSpice, Feb 2009, RGIT, Mumbai.

5. Analog Circuit Design, STTP Saraswati Engineering College, Kharghar, Navi Mumbai, July 2009.

6. Optimization of Transistor Performance for VLSI Applications, Tasgaokar College of Engineering, Karjat, Thane, April 2010.

7. Integrated Circuit Design using WinSPICE, Pooranmal Lahoti Government Polytechique College, Latur, 23rd Jan 2011.

8. How to write a Technical Paper, Don Bosco Institute of Technology, DBIT-IEEE Chapter, September 2011.

9. Role of Electronics & Telecommunication Engineers in 21st Century, Yadavrao Tasgonakar College of Engineering and Technology, Bhivpuri, Karjat. October 2011

10. Low Power VLSI Design, STTP, Lokmanya Tilak College of Engineering, Kopar Khairne, Navi Mumbai, 11th January 2012.

11. Variability Aware Performance Evaluation of Nanoscale CMOS Devices and Circuits, 10 March 2012, Technical Talk Delivered to DBIT faculty members as part of Staff Development Programme.

12. Past, Present, and Future of VLSI, Yadvarao Tasgaonkar Institute of Technology, Bhivpuri Road, Karjat, Thane, on 10 April 2012.

13. Optimization of Signal Processing Algorithms for Efficient Implementation of VLSI Architectures, STTP on Advances in Signal Processing, KIT, Kholapur, 4 January 2013.

14. Journeying from Electronics to Nanoelectronics, K. J. Somaiya Institute of Information Technology, Sion, Mumbai, 7 February 2013.

15. Advanced Low Power VLSI Design at Fr. Angel College of Engineering, Vashi, Navi Mumbai, July 2013.

16. In Search of research, Don Bosco Institute of Technology, Faculty Development Programme, January 10, 2014

17. CMOS Analog VLSI Design, Sandipani Institute of Technology, Nashik, February 2014.

18. How Write Project Report, K K Wagh College of Engineering, Nashik, May 2014.

19. Variability Aware Low Power Design of Nanoscale CMOS circuits, Saradar Patel Institute of Technology, Andheri(W), Mumbai, May 7, 2015.

20. Design of nanoscale Analog and Mixed Signal VLSI Design, Gujarat Technological University, Research Symposium, April 2015

21. VLSI Design: Road Map to Explore IoT and Multidimensional Opportunities, K.C. College of Engineering on September 22, 2015.

22. Design of MOS Differential Amplifier and Two stage Operation Amplifier, Sardar Pater Institute of Technology on December 9, 2015.

23. Statistical Techniques for the performance evaluation of Nanoscale COS devices and Circuits, Gujrat Technical University on April 12, 2016.

24. Nanoscale Low Power VLSI Design, Shah &Anchor College of Engineering, Chembur, Mumbai on July 1, 2016.

25. Low Power VLSI Design, MIT College of Engineering, Kothrud, Pune on July 4, 2016.

26. Electronics:Past, Present and Future, IEEE-WIE Outreach programme, DBIT on August 3, 2016.

27. Nanoscale Low Power Design using Design of Experiment Technique, Harne College of Engineering, B.R. Harne College of Engineering, Badlapur, on August 6, 2016.

28. Workshop of Next Generation Simulation Programme with Integrated Circuit Empasis (Ngspice), KC College of Engineering, Thane on December 19-20, 2016.

29. Low Power CMOS VLSI Design Technique, at the Universal College of Engineering, Vasai on March 7, 2018.

30. Career Opportunities in VLSI Design, at Vidyalankar Institute Technology, Mumbai on March 8, 2018.

31. VLSI Design - Past, Present and Future, at D. J. Sanghvi College of Engineering, Mumbai on March 23, 2018.

32. Advancement and Career Opportunities in Analog and Mixed Signal VLSI Design, at K.C. College of Engineering, Mumbai on April 02, 2018.

33. Bloom’s Taxonomy: Tool for Making Efficient Engineers, on December 20, 2018 at Don Bosco Institute of Technology, Mumbai.