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A day or two ago, my Moto G6 started showing an analog clock on the lock screen. There used to be a digital one. I am not seeing any corresponding settings under Display or Security/Lock screen. Not sure how this happened.

The person posting on that thread showed the schematic of a commercially available board using the LMK04832; I am using the same board but evidently an updated version with the 0.1uF capacitor added between OSCin_N and ground). I too an unable to get PLL1 to lock in dual-loop mode, and have confirmed it is only PLL1 that is not locking (PLL2 locks to the output of PLL1 even though PLL1 is not locked, since it is still approximately the expected frequency due to the limited tuning range of the VCXO). I have also confirmed this by trying both loop polarities and observing the VCXO tuning voltage on an oscilloscope. As expected it rails out to either 3.3V or 0.0V depending on the loop polarity. Do you have any other tips to get PLL1 to lock? I'm using 450uA CP gain but since the loop bandwidth is so low in the PLL1 loop filter (it has 0.1uF + 0.68uF loop filter capacitors), I didn't think it could be a stability / phase margin issue. I've attached my current draft of the tcs file.

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- The schematic is the same as in the prior post, except the 0.1uF to ground is included on OSCin_N as identified in that post, and the input reference crystal is now 12.288MHz instead of 10MHz. I believe it is just an updated version of the same design. No other differences of importance; just using different outputs. I am actually not having a problem with the outputs, for the most part, and see they are at approximately the right frequency since PLL2 is locked.

- I have double checked that I have selected the right input clock by trying override mode and saw no difference. I also just probed the sel pins: pin 59 (SEL1) is low and pin 58 (SEL0) is high as expected. (The "sel pol" bit is low, so these should be active-high controls, I believe).

- I have tried configuring CLKin0 to go directly into PLL2 and avoid PLL1 altogether. However, this causes PLL2 not to lock, I think because the 12.288MHz PFD frequency is too low relative to the CPout2 loop filter on this board. At least with PLL1 unlocked, I see that PLL2 is locked, but the PLL1 VXCO is just maxed out to its highest frequency, and its tuning voltage is also maxed out at about 3.25V rather than mid-rail.

Here's a capture of the two clocks (12.288MHz refclk and 122.88MHz VCXO), showing there is significant coupling of the VCXO onto the refclk. I wonder if that is enough to cause some issues with PLL1 and could try soldering another termination resistor to reduce the amplitude of the VCXO output.

Thanks for checking in your simulation tool. I tried with TI's "Clock Design Tool", but it does not support the LMK04832. I can try downloading PLLatinum Sim as well, and I will try replacing 39k -> 8.2k as you suggest.

Ah, I see with PLLatinum Sim that the 39k must be more appropriate for a 1.2288 MHz comparison frequency, so that's easier to change than reworking these boards. I'll add a reference divider (1x -> 10x) instead and see if that allows PLL1 to lock. I don't see where the tool reports phase margin, but at least it doesn't say "redesign filter?" when I use a 10x reference divider and the loop filter unchanged.

I've tried a variety of settings and still getting no locking behavior. As far as I can tell the only difference between this circuit and the PLL1 on the LMK04832 EVB is that this VCXO has 3.0kHz/V and the one on the EVB has 2.5kHz/V frequency tuning curve. This degrades PM slightly but isn't a big change. The EVB documentation says it has 50 deg PM, but when you plug in the values into PLLatinum, it shows 41 degrees. I have now lost PLL2 lock as well as PLL1 lock with the reduced PFD frequency (I've tried 600kHz and 1.024MHz just like in the EVB example). Next step might be to try a different resistor value, but I don't see why that should be necessary since the circuit clearly worked on TI's EVB...

As a test, can you enable holdover by setting HOLDOVER_EN, and enable exit from holdover based on LOS by setting HOLDOVER_EXIT_MODE=0 (Exit based on LOS), LOS_EN=1 and LOS_TIMEOUT=0 (5MHz)? I don't think this should impact the issue, but just in case the clock selection state machine has somehow gotten confused, this could help us check what's going on.

Thanks for the suggestions, I think I may have found a signal integrity issue on the reference clock using the PLL2_LD_MUX option you suggested. In my latest configuration, attached, I now see the VCXO tuning voltage spiking down from the 3.3V rail at random intervals, then returning. This looks like failed attempts to lock, so that's definitely some progress versus yesterday. I exported PLL1_N and PLL1_R to a status pin and I see square waves; but neither of them is a periodic clock. I assume that PLL_N (0x16E = 0x5B) is the output of the feedback divider set to div-120 and PLL_R (0x16E = 0x7B) is the output of the reference divider set to div-12. Given that the VCXO is being pulled all over the place I would expect PLL_N not to be very clean, but actually PLL_R is also not periodic (my oscilloscope can't lock to a repeating pattern, see a single capture below). Assuming PLL_R is the output of the reference divider I would expect a clean square wave at 12.288MHz / 12, so clearly there is a problem in the reference path to PLL1. I am sure that I am using the correct input because when I set CLKin_SEL_PIN_POL to invert the SEL0/SEL1 bits, I get no output on PLL_R. The fact that the PLL1 tuning voltage is moving around rapidly also explains why PLL2 is no longer able to lock, as it was previously when PLL1 Vtune was railed out.

I think I might desolder the 100ohm resistor bridging the differential 12.288MHz reference input clock, to try to increase that signal swing. It was apparent from prior measurements/posts that there was some coupling from the single-ended 122.88MHz VCXO onto the differential 12.288MHz reference signal, but PLL_R being aperiodic with a reference divider value of 12 seems suspicious to me. Does that seem like a correct conclusion?

Although the reference clock itself looks ok to me, so maybe I am misunderstanding what exporting PLL2_R does. You can see in the prior post that it is above above the expected 1.024MHz, basically showing "extra edges". The reference clock is shown below:

The exported signals out of the GPIO pins are the inputs to the PFD for that PLL, so I would nominally expect the signal from the PLL1 R and N = 1.024MHz. The PFD signals should definitely be periodic when the PLL is locked, and moreover the frequency should be very close to exact - 1.852MHz is completely wrong. Meanwhile, the N signal is a complete mess. Something very strange is happening to your PLL.

This is looking more like a power supply issue than a signal integrity issue, since as you've demonstrated the CLKin and OSCin signals appear to have clean edges. The PLL1 R signal should not be off-frequency, the PLL1 N signal should not be cutting out for long periods of time unless the circuitry is being disrupted in some unexpected way, and I would expect PLL2 to lose lock if the OSCin buffer is failing (you stated you could get PLL2 to lock at some point prior, but it seems that PLL2 lock has started failing as well at some point?), so there may be an issue with the voltage at the OSCin, PLL1, or digital supply pins cutting out. You could probe the pins for those supplies to check if the voltage is stable.

I figured out something that works, by accident! While trying to set the PLL2_LD_MUX to 0x5B to configure the observation mux, I accidentally set another register I have been messing with, 0x146, to 0x5B. This actually locked! I determined that the problem was setting CLKin_SEL_PIN_EN = 1.

If I change my configuration from 0x146 = 0x98 to 0x146 = 0x18 (or anything else with the MSB = CLKin_SEL_PIN_EN = 0), then it locks! I can't explain this based on anything in the datasheet, so it must be that the CLKin_SEL_PIN mode is not working. I have probed pins 59 and 58 again and confirmed they are stable and in the correct logic state (59 = SEL1 is low, 58 = SEL0 is high). I don't know if I have a misconfiguration related to CLKin_SEL_PIN_EN, or I have a defective chip, or there is some bug in the implementation of pin-selecting clocks. But now that I figured it out I can just avoid CLKin_SEL_PIN_EN = 1 and it should work fine for our uses.

I should add that since observing the pin select at the package level showed they are quiet, and the input-select was clearly toggling on and off creating those bursts of edges, it seems like the issue could be due to an on-chip coupling path. Could you ask the LMK04832 layout designer to look at those nets and see if it might be toggling due to a nearby large clock signal or due to sharing a power supply with a nearby clock driver?

It occurs to me that the pin select decode table is actually missing from the LMK04832 datasheet. It inherits the function from the LMK0482x family, which shows that for CLKin_SEL0 = H and CLKin_SEL1 = L, it should select from CLKin1. However, setting 0x01465B selects CLKin0 manual. Try setting CLKin_SEL0 to a pull-down and re-enable CLKin_SEL_PIN_EN, does this lock?

I can try that a bit later today. This might warrant a new thread since I marked this one as resolved, but I am seeing more of this toggling on/off behavior, this time with the outputs instead of the reference select. I think you might be right that it points to a marginal supply or some coupling path. With my last configuration (1 LVDS output and various 2V LVPECL outputs), I see the ~200MHz output being toggled on/off at the 10MHz sysref frequency. This seems somehow related to the input clock-select being toggled on/off and even the PLL_N output apparently toggling on and off. I'm suspecting a bad supply network. My first step is to reduce the 2V LVPECL outputs to 1.6V. I was thinking I could skew the phase of the outputs as well, to even out the supply draw (like you might see in a multiphase buck converter). This particular board is set up to generate 3x 10MHz SYSREF outputs on OUT0, 3, 5, and 5x 200 MHz on OUT1, 2, 4, 6, 8. One of those is unnecessary and can be turned off, but this seems like a similar issue to the reference clock problem above except this time at the output. ff782bc1db