Diogo Brito was born in 1987 in Lisbon, Portugal. He received the M.Sc. and Ph.D. degree in Electrical and Computers Engineering from Instituto Superior Técnico (University of Lisbon), Portugal, in 2012 and 2018 respectively .

From July 2012 to the present day, he has been a research grant holder at Instituto de Engenharia de Sistemas e Computadores - Investigação e Desenvolvimento (INESC-ID), in Lisbon, Portugal. Currently, he is also an invited assitant professor at Escola Superior Náutica Infante D. Henrique.

His current research interests include analog and RF circuits, with emphasis on RF frontends and their constituting blocks, and digital signal processing, with emphasis on techniques to detect extremely weak signals in noisy environments.

• Email: diogo.brito [at] inesc-id.pt
• Tel.: +351-213 100 374

PhD in Electrical and computer engineering at Instituto Superior Técnico (2014-2018)

• Thesis title "Radio Pulsar System for Navigation" - link

MsC in Electrical and Computer engineering at Instituto Superior Técnico (2005-2012)

• Thesis title "Quaternary Logic Look-up Table" - link

Electrical/Electronics Maintenance and Repair Technology (2002-2005)

• J. Palma, D. Brito, G. Tavares, , J. Fernandes. "Radio Pulsar Signal Generator", IEEE International Symposium on Circuits & Systems, May, 2018.
• D. Brito, J. Palma, G. Tavares, , J. Fernandes. "Live Demonstration: a Pulsar Signal Receiver System for Navigation", IEEE International Symposium on Circuits & Systems, May, 2017.
• G. Tavares, D. Brito, J. Fernandes. "A Study on the Accuracy of Radio Pulsar Navigation Systems", European Navigation Conference, Apr., 2015.
• D. Brito, G. Tavares, J. Fernandes, A. Noroozi, C. Verhoeven. "Radio Pulsar Receiver Systems for Space Navigation", European Space Agency (ESA), 8th European Symposium on Aerothermodynamics for Space Vehicles, Mar., 2015.
• D. Brito, T. Rabuske, J. Fernandes, P. Flores and J. Monteiro, “Quaternary Logic Lookup Table in Standard CMOS”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 306-316, Mar., 2014
• T. Rabuske, F. Rabuske, J. Fernandes, C. Rodrigues, D. Brito, “Comparator-based Binary search ADC Architectures for UWB Receivers”, Analog Integrated Circuits and Signal Processing 77 (3), 471-482, Dec., 2013.
• D. Brito, J. Fernandes, P. Flores and J. Monteiro, “Standard CMOS Voltage-mode QLUT Using a Clock Boosting Technique”, 11th IEEE International New Circuits and Systems Conference (NEWCAS), pp. 1-4, Jun., 2013.
• D. Brito, J. Fernandes, P. Flores and J. Monteiro, “Design and Characterization of a QLUT in a Standard CMOS Process”, 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 288-291, Dec., 2012.