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Debjit Sinha is currently an engineer at Google working on chips/ML/cloud. He has previously been a Senior Engineer/Scientist at IBM Systems [Electronic Design Automation group], New York, USA (2006-2020) and an appointed member of the IBM Academy of Technology. His work as well as broad research and development interests include algorithms and statistical modeling/analysis/optimization for VLSI Computer-Aided design (CAD). This includes: Statistical timing analysis/optimization, crosstalk noise analysis/optimization, timing macro-modeling/abstraction, distributed and multi-threaded analysis, machine learning for VLSI CAD, and electrical circuit analysis. He has been the overall technical lead for the (cross geography) IBM timing analysis and timing abstraction team (IBM's flagship timing tool EinsTimer/EinsStat). Debjit obtained the Ph.D. degree in Electrical and Computer Engineering from the ECE department at the Robert R McCormick School of Engineering and Applied Sciences, Northwestern University, USA in 2006, and a B.Tech. from the Indian Institute of Technology at Kharagpur, India in 2001.

Awards and professional service

  • Appointed to IBM Academy of Technology

  • ACM SIGDA Editor-In-Chief for e-newsletter (2020-present), associate editor (2008-19)

  • 8 IBM patent invention plateau awards (Two most recent awards: 8th plateau - April 2020, 7th plateau - April 2019)

  • 2 IBM outstanding technical achievement awards (OTAA) on Statistical multiple input switching (2019) and statistical timing deployment in IBM server flows (2012)

  • IBM TEC/TechConnect best paper/presentation awards (2017, 2016, 2014, 2011, 2010, 2009)

  • 3 ACM awards for outstanding contributions to TAU and SIGDA (2016, 2015)

  • IBM high value patent award for work on crosstalk aggressor filtering (2010)

  • Panel organization - TAU 2019 (Multiple input switching impact on timing), TAU 2018 (Machine learning: Confluence with timing/EDA)

  • TAU conference: General chair (2016), technical program chair (2015), program committee member (2013-present)

  • Started TAU software contest: Contest chair (2013), contest committee (2013-16)

  • Technical program committee member - ICCAD 2009/12/13

  • Reviewer for IEEE TCAD, TVLSI journals, and conferences including ICCAD and DAC, session chair for multiple conferences

  • Senior member, IEEE


Panelist roles and invited talks

  1. Post silicon reality vs. pre silicon modeling - TAU 2019 panel

  2. Silicon aging effects: Modeling and analysis - TAU 2017 panel

  3. Timing challenges in building a modern day microprocessor - Invited talk at EECS, Northwestern University, Evanston, IL, USA (2016)

  4. Variability in timing: Where is statistical timing? - TAU 2013 panel