RSVP - Reception & Dinner: We have 50 spots (first come first serve)
https://forms.gle/2abirmj8ocUvGehn9
Diner Time: 6:00PM, June 21st 2025
Diner Location: Uni. Cafe 125, Just next of Okuma Auditorium
Program at a glance
https://docs.google.com/spreadsheets/d/19-xsSZfdN44cE3y2yNMdaAKaTA7v5cR922Yy8hr-Fec/edit?usp=sharing
Abstracts
https://docs.google.com/spreadsheets/d/1PCAZ1gb9LaH5CMkVrjti-g9rh3bhajgaOYSO17uHmRY/edit?usp=sharing
Panel: Transformational improvements in data center power efficiency and sustainability
In this panel, industry and academic leaders share their vision and work towards more sustainable data centers, especially with exploding demands for AI performance. Panelists will present on the latest development in power efficiency at their institutions including breakthroughs in software, hardware and software/hardware co-design. The presentations will be followed by a Q&A session.
Panelists Biographies: Brijesh Warrier (Microsoft), Zane Ball (Advisor, Z Insights LLC, Tawfik Arabi (AMD), Lizy John (UT-Austin), Anupam Thakur (Microsoft)
https://docs.google.com/document/d/1t0pGF-Um5IMWXs8H6kWO2pMqAYVVGvALwPW7hncsccs/edit?usp=sharing
The rapid advancement of artificial intelligence (AI) algorithms, particularly large language models, is significantly increasing the computing demands in modern data centers. Meeting the projected performance requirements over the next 5 to 10 years has profound implications for global energy consumption, with some estimates suggesting that data centers could account for over 20% of worldwide energy usage. Addressing this trend necessitates innovation across various domains and collaboration among industry, academia, and governments.
The 1st International Workshop on Data Center Energy Efficiency (DCEE-2025) aims to tackle the power and energy challenges that data centers will face in delivering the anticipated AI performance over the next decade. The primary objective of this workshop is to convene the latest research and development efforts from academia, industry, and governments, fostering closer collaboration to advance these technologies.
Workshop Topics Include (but not limited to) the areas below
■ Innovations in software and hardware for data center power management
■ Power management for CPUs, GPUs, and domain-specific accelerators
■ Advances in power delivery across dies, packages, boards, racks, clusters, and data centers
■ Efficient energy transfer from power sources to data centers
■ Telemetry for power and energy management in components and systems
■ Optimization of power and energy for data movement
■ Development of power-efficient algorithms
■ Co-optimization of hardware and software for energy efficiency
■ Optimization of power and energy interconnects and packaging
■ Cooling technologies for ASICs, boards, racks, and data centers
We invite you to submit a paper and/or join us at DCEE-2025 co-located with ISCA 2025 to share your insights and collaborate on pushing the boundaries of data center energy efficiency.
Submission Details:
■ Paper format: 1 to 2 pages (standard IEEE/ACM two column format)
■ Submission Deadline: 19 May 2025. Author notification by 23 May 2025
■ Submission site: https://easychair.org/conferences?conf=dcee2025
■ Awards: Best Student Paper Award; Best Presentation Award; Best Paper Award
Organizing Committee
Tawfik Arabi, AMD, Program Chair
Tawfik is a Fellow technologist at AMD, currently responsible the power efficiency of GPUs. Prior to that, he was a senior principal architect at Microsoft where he developed co-optimized HW/SW solutions to improve the power efficiency of Microsoft data centers and a Sr. Principal engineer at Intel corporation where he worked on optimizing Intel Laptops and desktops delivering innovations and contributions in performance, power, and power delivery. He has a Ph.D. in electrical engineering from Syracuse University.
Tawfik is the recipient of many Company and IEEE awards including 6 Intel Achievement award. He is an IEEE fellow and has well over 100 external Journal and conference publications and over 30 patents. He taught classes at Portland State University, Oregon State University, and Oregon Graduate Institute. He supported and directed research programs with several leading universities. His external publications and patents can be found at https://scholar.google.com/citations?user=xPFZ-boAAAAJ&hl=en
Lizy John, UT-Austin, Co-chair
Lizy Kurian John is Truchard Foundation Chair in Engineering at the University of Texas at Austin. She received her Ph. D in Computer Engineering from the Pennsylvania State University. Her research interests include workload characterization, performance evaluation, memory systems, reconfigurable architectures, and high-performance architectures for emerging workloads. She is recipient of many awards including Joe J. King Professional Engineering Achievement Award (2023), The Pennsylvania State University Outstanding Engineering Alumnus Award (2011), the NSF CAREER award, UT Austin Engineering Foundation Faculty Award, Halliburton, Brown and Root Engineering Foundation Young Faculty Award, University of Texas Alumni Association (Texas Exes) Teaching Award, etc. She has coauthored books on Digital Systems Design using VHDL (Cengage Publishers, 2007, 2017), a book on Digital Systems Design using Verilog (Cengage Publishers, 2014) and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. She holds 18 US patents and is an IEEE Fellow (Class of 2009), ACM Fellow, AAAS Fellow and Fellow of the National Academy of Inventors (NAI).
Anupam Thakur, Microsoft, Co-chair
Anupam Thakur is the Director of Strategic Planning for AI Infrastructure at Microsoft. In this role, Anupam spearheads innovative strategies to optimize AI infrastructure, ensuring cutting-edge performance and eficiency. Before joining Microsoft, he was at AMD, where he made signiicant contributions to optimizing the power and performance of the Instinct line of Datacenter GPUs. Anupam has a strong background in Mixed-signal design, Signal integrity and Serdes technology which has allowed him to drive technological advancements in the AI Infrastructure.
Anshuman Mittal, NVIDIA, Co-chair
Anshuman Mittal is an accomplished Technology Professional with over 25 years of experience specializing in the power, performance, and design of Graphics Processors, Microprocessors, and SOCs. Currently serving as an architect at NVIDIA, he plays a crucial role in driving performance-per-watt eficiency for memory subsystems across AI datacenter, gaming, and integrated GPUs. Prior to his tenure at NVIDIA, Anshuman held various positions at industry giants including AMD, Samsung, Oracle, and Broadcom and was instrumental in developing next-generation power/performance architectures and design for GPUs and CPUs. He holds a Master's degree from Santa Clara university and has published multiple papers & patents in the domain.
Technical Program Committee (WIP)
Tawfik Rahal-Arabi AMD
Koji Inoue Kyushu University
Anupam Thakur Microsoft
Lizy John UT Austin
Peter Debock US Department of Energy
Mo Bashir Intel
Mehdi Sadi AMD
Indrani Paul AMD
Anshuman Mittal Nvidia
Esha Choukse Microsoft
Patricia Gonzalez-Guerrero OCP
Ahmed Shams Intel
Arman Shehabi Lawrence Berkeley National Laboratory
Carole-Jean Wu Meta
Ravi Mahajan Intel
Bo Wang Singapore University
Ping-Hsuan Hsieh National Tsing Hua University, Taipei
Vidyasagar Ganesan AMD
Navid Farazmand Google