In-Memory Computing

Emerging devices, architectures, and applications

September 13, 2018 - Politecnico di Torino (Italy)

Program

A full-day workshop dedicated to In-Memory Computing with Emerging Devices. Attendees will be introduced to the most recent advances on the field, from new devices and their physics, to new integration strategies and possible applications and use-cases.

Schedule

[09.15 - 09.45] Registration

[09.45 - 10.00] Opening

Session 1: Emerging Devices

10.00 - 10.40 Markus Becherer, Magnetic computation: visions from a fabricational perspective?

10.40 - 11.20 Giulia Lucarelli, Perovksite solar cells architectures for solar cells and memristive devices

11.20 - 12.00 Felipe Garcia-Sanchez, Skyrmion dynamics and devices

[12.00 - 13.30] Lunch and Networking

13.30 - 14.00 Industry Keynote by Micron Technology, Inc.

Memory Devices: Status, Outlook and Challenges, Innocenzo Tortorelli, Fabio Pellizzer and Paolo Amato

Session 2: Architectures

14.00 - 14.40 Anupam Chattopadhyay, Local computing: Battles with parallelism

14.40 - 15.20 Shahar Kvatinsky, Real Processing-in-Memory with Memristive Memory Processing Unit

15.20 - 16.00 Fabrizio Riente, Logic-In-Memory Computing: Exploiting the Monolithic 3D Integrability of pNML Technology

[16.00 - 16.30] Coffee Break

Session 3: Applications

16.30 - 17.10 Gyorgy Csaba, Computing with coupled oscillators

17.10 - 17.40 Damien Querlioz, ​In-Memory Computing: Lessons from the Brain

17.40 - 18.20 Marco Ottavi, Power in logic: using memristors in photovoltaic arrays, a use case

[18.20 - 18.30] Closing Remarks

Registration

The DANTE project embraces the open-source philosophy. Participation is free of charge and open to anyone interested in the topic. Due to organizational issues, we kindly invite people to sign-in if they really intend to participate.

Fill-in the registration form

Registration deadline: 3 September 2018 (available seats are limited, policy: first-come/first-served)

Organizers

Andrea Calimera

Politecnico di Torino

Department of Control and Computer Engineering

C.so Duca degli Abruzzi 24, 10129 Torino – ITALY

Marco Vacca

Politecnico di Torino

Department of Electronics and Telecommunications

C.so Duca degli Abruzzi 24, 10129 Torino – ITALY

Location

Department of Electronics and Telecommunications (DET) - Room Maxwell

Politecnico di Torino,

Corso Castelfidardo, 42 - 10129, Torino (Italy)

Detailed instructions on how to reach the conference room with local transportation

Travel

By Plane

Caselle International Airport allows daily connections with the main European cities. The SADEM bus company connects the airport to the city center. The cost is 7,50€ and tickets are available on board. Buses stop at both Porta Nuova and Porta Susa railway stations. Both are walking distance to the Politecnico campus, with Porta Susa being the closest one. Taxi service is also available with fares around 30€ to Torino city center, and about 35€ to the Politecnico campus. Alternatively, Malpensa International Airport is one of the main European hubs connected to more than 120 cities all over the world.

By Train

Torino has two main railway stations: Porta Nuova and Porta Susa. Both stations are located in the city centre, very close to the Politecnico di Torino. They are connected with frequent high speed rail services to main destinations in Italy and France, and from there to the rest of Europe. More information are available at the Trenitalia website.

By Car

Motorways A6 Torino-Savona, A4 Torino-Milano-Venezia, A21 Torino-Piacenza-Bologna, A5 Torino-Aosta, A32 Torino-Bardonecchia connect Torino to most Italian and European cities.

Invited Talks

Session 1: Device

Magnetic computation: visions from a fabricational perspective?

Markus Becherer, Technical University of Munich (TUM)

Abstract - Digital computation with ferromagnetic multilayer islands is one promising technology in beyond CMOS device research. In the physical implementation of the so-called perpendicular Nanomagnetic Logic (pNML), it provides intrinsically non-volatile computational states, atto-joule dissipation per bit operation and CMOS competitive data-throughputs. Rather than CMOS substitution, additional functionality is added by a co-processor architecture as a prospective back-end-of-line (BEOL) process. In this work, the platform of monolithically 3D integrated pNML is reviewed and challenges in terms of fabrication and system operation are discussed.

Speaker biography - Markus Becherer currently is provisional head of the Chair of Nanoelectronics at Technical University of Munich (TUM). He received the Diploma degree in electrical engineering from Technical University of Munich in 2005. In 2011, he graduated as Dr. Ing. from TUM and was awarded with the Kurt-Fischer-Preis for an outstanding dissertation. After graduation, he was leader of the research group for nanomagnetic logic at the Chair of Technical Electronics. Since 2017 he is Adjunct Teaching Professor at the TUM Department of Electrical and Computer Engineering. His research interests are fabrication technologies of nanostructures and advanced magnetic devices for sensing and computation.


Perovksite solar cells architectures for solar cells and memristive devices

Giulia Lucarelli, University of Rome Tor Vergata

Abstract - Perovskite solar cells have shown the potential to deliver high efficiency, easy processing and manufacturability. We will review the main benefits of this technology which can combine ease of processing (i.e. via printing and evaporation techniques) with high power conversion efficiencies (which currently stands at over 22% under standard test conditions, i.e. the sun). We will also present research focused at developing device architectures and materials, including novel solution-processed transport layers, that produce devices with remarkable performance under artificial indoor illumination. Finally, we will briefly introduce the possibility of using the perovskite solar cell architecture or a combination of its layers to develop memristive devices.

Speaker biography - Giulia Lucarelli carried out her undergraduate studies in Industrial Chemistry at University of Rome "La Sapienza". After graduating cum laude in Material Science and Technology at University of Rome "Tor Vergata", she obtained a Marie Curie Early Stage Researcher position at University College London, where her work was focused on the optimization and characterization of near-infrared organic photodetectors. She is currently a PhD candidate at University of Rome "Tor Vergata" working at the Center for Hybrid and Organic Solar Energy (CHOSE) on flexible and stretchable perovskite solar cells for indoor and outdoor applications.


Skyrmion dynamics and devices

Felipe Garcia-Sanchez, Istituto Nazionale di Ricerca Metrologica (INRIM)

Abstract - Skyrmion are magnetic structures that constitute tyny swirls of the magnetization in ferromagnetic thin layers. Due to their stability and low sensitivity to defects, they have been proposed as future magnetic recording media, where such magnetic particles are the bits that can be moved with electrical current. In this talk I will present the numerical simulations of two possible Skyrmion devices which we have proposed for other potential applications. The first is the GHz oscillation of Skyrmions inside nanodisks, which can be used for oscillators tuned by current. The second is the use of Skyrmions to perform conservative logic.

Speaker biography - Dr F. Garcia-Sanchez obtained his PhD in Condensed Matter Physics in 2007 from Universidad Autonoma de Madrid. After that he has done several postdocs in Spintec (Grenoble), Research Center Juelich and Université Paris-Sud. He is an expert in simulation of magnetization dynamics. Since 2016, he is Assegnista di Ricerca at INRIM.


Keynote

Memory Devices: Status, Outlook and Challenges

Innocenzo Tortorelli, Micron Technology, Technology Development, Vimercate (MB), Italy

Fabio Pellizzer, Micron Technology, Technology Development, Boise (Idaho), United States

Paolo Amato, Micron Technology, Mobile Business Unit, Vimercate (MB), Italy

Abstract - The memory field today represents a large part of the overall semiconductor market and it is becoming more and more relevant due to the continuous demand of storage capability coming from the usage of electronic devices in many different areas of human life. It is worth noting that today memory is considered one of the most important factors to justify the cost of electronic devices, for example smart phones or tablets. In electronic systems, memories are classified between volatile and non-volatile depending on their ability to retain information when power supply is off. DRAM and SRAM are the mainstream technologies for volatile memory. They are, in general, directly interfaced with the logic unit and they have high performances but high cost. NAND FLASH is the main stream technology for non-volatile memory and they are mainly used for data storage, being lower performer and lower cost. In the past few years, a new memory segment (named Storage Class Memory, SCM) has been proposed as an effective way to improve the overall performance of the system. PCM (Phase Change Memory) appears to be an ideal candidate for this purpose. In this talk, starting from actual mainstream technologies, the different kind of memories will be reviewed. Their limitations will be analyzed as well as possible ways to overcome them. Finally, new memory concepts capable of realizing the SCM will be presented and their main challenges highlighted.

Speaker biography - Innocenzo Tortorelli is a Senior Member of the Technical Staff at Micron Technologies, where he works in technology development of emerging memory devices and new array architectures for next generation high density memory products. He got his Laurea degree in electrical engineering from Politecnico di Torino (Italy) in 2002, and a specialization course in electrical communications from Galileo Ferraris institute (Italy) in 2004. Fabio Pellizzer received his Laurea degree in Electronic Engineering in 1996 from the University of Padova, Italy. He is a Distinguished Member of Technical Staff at Micron Technologies and he is responsible for process development and electrical characterization of new emerging memory cells. He has authored many papers and conference contributions, for a total of 5326 citations and an H-index equal to 31. He has authored 125 granted US patents. Paolo Amato is a Distinguished Member of the Technical Staff at Micron Technologies, where he investigates storage and memory architectures (based on mainstream and emerging technologies) for next generation mobile systems. He is an expert on statistical methods, error correcting codes and security. He got his Laurea degree in computer science from University of Milano (Italy) in 1997, and his PhD in computer science from University of Milano-Bicocca (Italy) in 2013.

Session 2: Architecture

Local computing: Battles with parallelism

Anupam Chattopadhyay, Nanyang Technological University (NTU)

Abstract - The free lunch of Moore's law overshadowed innovations in the computer architecture for the better part of past 50 years. Realizing the inevitable decline of the transistor scaling, there is a newfound enthusiasm to explore alternative computing devices, with matching support from the computer architects to quench the never-ending demand for energy-efficiency. In this talk, first, we will revisit the development of computer architectures from the peephole of computational parallelism and data/computation locality, starting from the early ideas of data-dependency, data-level parallelism, and application-specific processors, to the new era of in-memory computing. In the second part, we will see how the proposed in-memory computing architectures are garnering the support of robust design automation flows. The talk will conclude with the long-term vision of exploiting the device-level efficiency, for which, some early results in ternary arithmetic and multi-valued logic will be presented.

Speaker biography - Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India, MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2000, 2002 and 2008 respectively. From 2008 to 2009, he worked as a Member of Consulting Staff in CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group in RWTH Aachen, Germany as a Junior Professor. Since September, 2014, he is appointed as an assistant Professor in SCSE, NTU and also holds an honorary adjunct appointment at SPMS, NTU. In the past, he was visiting Professor at EPFL, Switzerland and Indian Statistical Institute, Kolkata. During his doctoral studies, he worked on automatic RTL generation from the architecture description language LISA, which led to a spin-off, and subsequently was acquired by a leading EDA vendor. Anupam currently heads a team of 20+ researchers, overseeing projects in the area of hardware accelerators, security, design automation and emerging technologies. He is a series editor of Springer book series on Computer Architecture and Design Methodologies. Anupam received Borcher's plaque from RWTH Aachen, Germany for outstanding doctoral dissertation in 2008, nomination for the best IP award in the ACM/IEEE DATE Conference 2016 and nomination for the best paper award in the International Conference on VLSI Design 2018.


Real Processing-in-Memory with Memristive Memory Processing Unit

Shahar Kvatinsky, Technion Israel Institute of Technology

Abstract - Computers have been built for many years in a structure where data is processed and stored using separate units – the processor and the memory. However, emerging applications such as artificial intelligence and internet-of- things require ample amount of data to be processed from numerous origins. This forces enormous data movement that becomes the main limitation in modern computing systems. Not only that the speed of computers is limited by this data movement, but also the energy consumption is mostly because of this transfer rather than the computation itself. An attractive approach to alleviate the data movement problem is to process data inside the memory. Unfortunately, contemporary memory technologies are ill-suited for such approach. Memristive technologies are attractive candidates to replace conventional memory technologies, and can also be used to perform logic and arithmetic operations using a technique called 'stateful logic.' Combining data storage and computation in the memory array enables a novel non-von Neumann architecture, where both the operations are performed within a memristive Memory Processing Unit (mMPU). mMPU relies on adding computing capabilities to the memristive memory cells without changing the basic memory array structure, and by that alleviating the primary restriction on performance and energy in modern computers. This talk focuses on the various aspects of mMPU. I will describe how memristors can be used for processing-in-memory and how it can be scaled as a wide SIMD like architecture. Later, I will show how different sequences of computing operations in an mMPU can be automatically optimized as sequences of basic Memristor Aided Logic (MAGIC) NOR and NOT operations. I will finalize by discussing the mMPU architecture and implications on the computing system and software, as well as examining the microarchitectural aspects.

Speaker biography - Shahar Kvatinsky is an assistant professor at the Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion – Israel Institute of Technology. He received the B.Sc. degree in computer engineering and applied physics and an MBA degree in 2009 and 2010, respectively, both from the Hebrew University of Jerusalem, and the Ph.D. degree in electrical engineering from the Technion – Israel Institute of Technology in 2014. From 2006 to 2009 he was with Intel as a circuit designer and was a post-doctoral research fellow at Stanford University from 2014 to 2015. Kvatinsky is an editor of Microelectronics Journal and has been the recipient of the 2015 IEEE Guillemin-Cauer Best Paper Award, 2015 Best Paper of Computer Architecture Letters, Viterbi Fellowship, Jacobs Fellowship, ERC starting grant, the 2017 Pazy Memorial Award, the 2014 and 2017 Hershel Rich Technion Innovation Awards, 2013 Sanford Kaplan Prize for Creative Management in High Tech, 2010 Benin prize, and six Technion excellence teaching awards. His current research is focused on circuits and architectures with emerging memory technologies and design of energy efficient architectures.


Logic-In-Memory Computing: Exploiting the Monolithic 3D Integrability of pNML Technology

Fabrizio Riente, Politecnico di Torino

Abstract - The third dimension is barely exploited in electronic circuits. Transistors are placed on the lowest layer, while additional layers are used only to route interconnections. This is a limit imposed by MOSFET technology and its fabrication process. With the arise of several new information technologies it is now possible to go beyond this limit. Perpendicular NanoMagnet Logic (pNML) intrinsically allows the design and fabrication of 3D circuits, enabling the possibility to place logic, memory and interconnection elements on each layer. Considering that the basic components of pNML technology are nanomagnets, each of them can act both as a logic and memory element. All these features enable to break the traditional bonds that limits the design of electronic circuits, allowing the creation of extremely compact 3D Logic-In-Memory circuits. In the first part of this talk we will analyze 3D pNML circuits, starting from the logic functions that can be implemented to the physical placement of each device, but considering also the on-chip integration of the clock generation network. In the second part, a pNML architecture that implements the Summed Area Table algorithm, one of the most common in image processing, is described and its performance analyzed. This kind of algorithm is a perfect candidate for this technology, since it requires only local interconnections between logic elements, thus leading to extremely compact circuits with embedded memory and logic.

Speaker biography - Fabrizio Riente received his M.Sc. Degree with honors (Magna Cum Laude) in Electronic Engineering in 2012 and the Ph.D. degree in 2016 from the Politecnico di Torino. He was Postdoctoral Research Associate at the Technical University of Munich in 2016. He is currently Postdoctoral Research Associate at the Politecnico di Torino. His primary research interests are device modelling, circuit design for nano-computing, with particular interest on magnetic QCA. His interests cover also the development of EDA tool for beyond-CMOS technologies, with the main focus on the physical design.


Session 3: Applications

Computing with coupled oscillators

Gyorgy Csaba, Pázmány Péter Catholic University

Abstract - Oscillator-based computing architectures use the phase or frequency of oscillatory signals to represent analog signals and they exploit the nonlinear interaction of oscillators for computing or signal processing. Such computing devices were invented decades ago, but currently they are making a comeback for two reasons: novel nanoscale oscillators may make excellent hardware for oscillatory computers, and in addition to that, oscillator-based computing protocols lend themselves naturally to neuromorphic algorithms. My talk will introduce three different approaches for doing computing with oscillators. The first approach uses spin-torque oscillators to accelerate vector-distance calculation, which is an often-needed step in image processing pipelines. The second approach uses parametrically pumped for ring oscillators in a Hopfield-network like associative memory. Finally, I will discuss the potential of oscillatory computers for addressing computationally hard (possibly NP hard) problems.

Speaker biography - György Csaba received the M.S. degree from the Technical University of Budapest in 1998 and his PhD degree from the University of Notre Dame in 2003. After working as a research assistant at the Technical University of Munich, Germany, he joined the faculty of the Department of Electrical Engineering of the University of Notre Dame (from 2010-2016), and he is currently an associate professor at the Pazmany Peter Catholic University in Budapest, Hungary. His research interests lie in modeling of nanoscale computing systems, Nanomagnetic Logic, spin electronics, physical cryptography and unconventional computing devices.


​ In-Memory Computing: Lessons from the Brain

Damien Querlioz, University of Paris-Sud

Abstract - In-memory computing is often presented as the ideal paradigm for energy-efficient artificial intelligence. This vision is largely due to the brain, which can be seen as a champion of in-memory computing. In this talk, we will look at neuroscience inspiration to extract lessons on the design of in-memory computing systems. In particular, we will study the reliance of the brain on approximate memory strategies, which can be reproduced in deep learning hardware. And we will see the brain uses the physics of its memory device in a way that is much richer than only storage. This can inspire radical electronic designs, where memory devices become a core part of computing. I will illustrate this concept by two works using spin torque memories, one inspired by the visual cortex, and one by the concept of reservoir computing.

Speaker biography - Damien Querlioz received his predoctoral education at Ecole Normale Supérieure, Paris and his PhD from Université Paris-Sud in 2008. After postdoctoral appointments at Stanford University and CEA, he became a permanent researcher at the Centre for Nanoscience and Nanotechnology of Université Paris-Sud. He focuses on novel usages of emerging non-volatile memory, in particular relying on inspirations from biology and machine learning. Damien Querlioz coordinates the INTEGNANO interdisciplinary research group. In 2016, he was the recipient of an ERC Starting Grant to develop the concept of natively intelligent memory. In 2017, he received the CNRS Bronze medal.


Power in logic: using memristors in photovoltaic arrays, a use case

Marco Ottavi, University of Rome Tor Vergata

Abstract - Fault tolerant Photovoltaic array used for green energy systems is emerging as an important area of study because of growing emphasis on reliable design. Among various photovoltaic cells Dye Solar Cell (DSC) is a promising low-cost photovoltaic (PV) technology and high energy-conversion efficiency. Recently it has been shown that it has memristive behavior as well. To efficiently support this claim, in this paper we use experimental data to characterize DSC cell and show that it exhibits memristor state behavior and developed a SPICE model. We use memristive DSC cells as sensing devices. This enables us to identify faulty cells in regular DSC. First, we present the model from the experimental data. A search algorithm is defined to identify the faulty components of the DSC array that fulfill the first requirement of a fault tolerant design. The proposed diagnosis method utilizes recently proposed fault detection solution for efficient testing of PV cells in the presence of faults. We divide the array into segments such that any faults is detectable thereby achieving high diagnosis accuracy.

Speaker biography - Marco Ottavi is currently an Associate Professor at the University of Rome Tor Vergata, before he was a Research Professor with the same University as the recipient of a “rientro dei cervelli” fellowship awarded by the Italian Ministry of University and Research. He previously worked as a Senior Design Engineer at AMD and held post doc positions with Sandia National Laboratories and with the Department of Electrical and Computer Engineering of Northeastern University in Boston. He received the Ph.D. in Microelectronics and Telecommunications Engineering from University of Rome “Tor Vergata” and the Laurea degree in Electronic Engineering from University of Rome “La Sapienza”. His research interests include yield and reliability modeling, fault-tolerant architectures, on-line testing and design of nano scale circuits and systems. From December 2011 to November 2015 he has been the Chair of COST Action IC1103 "Manufacturable and Dependable Multicore Architectures at Nanoscale" (MEDIAN). He is a Senior Member of the IEEE.