CPE 487-A

[12 - 02- 2021] I completed Lab 6 for this course, and was able to finish uploading some of the modified code into GitHub in my own repository. I plan to speak with my lab advisor to see if I can upload any of the work I have done onto the course website.

[11 - 16- 2021] I started Lab 6 for this class. I am having trouble seeing the ball output on the screen and having it move across.

[11 - 16- 2021] I completed Lab 5 for this class, which was a DAC Siren that generated a wailing audio siren using a 24-bit DAC. I also applied the modifications provided on GitHub.

[11 - 09- 2021] I completed Lab 4 for this class, which was a hex calculator. The FPGA was programmed to function as a simple hexadecimal calculator capable of adding and subtracting four-digit hexadecimal numbers using a 16-button keypad module.

[11 - 09- 2021] I completed Lab 3 for this class. I was able to set up the ViewSonic display and see a red square move across the yellow screen. I had some difficulties last class to have the display show on the screen, and I realize there was an error in my vga_sync file which I was able to fix today. I also ran the ball_1 modification on GitHub, which features a ball bouncing across the whole screen in random order.

[11 - 05- 2021] I completed my first milestone in the Quantum FPGA Lab. I used VHDL and Vivado to simulate a counter using the ZedBoard. My next task for the next week will be to implement a binary counter, utilizing the buttons and LED display on the board.

[10 - 21- 2021] I have completed Lab 2 for this class. I was able to set up the eight- digit hex counter on the FPGA in class today. The counter module generates a 16-bit count value using bits 23 to 28 of the 39-bit binary counter at a frequency of 100MHz/2^23 ~= 12 Hz

[10 - 19 - 2021] I have completed Lab 1 for this class. I was able to set up the binary number counter, and see the hex digits 0 through F cycle through on the display board.

[10 - 07 - 2021] I have completed Exercise 1 of this document. This helped me learn how to set up a project in Vivado.

[10 - 06 - 2021] I have completed most of Assignment 2: VHDL Test Bench. I used an online VHDL guide to find the VHDL code I would like to test. The code is a simple half-adder function. I was able to use the example testbench the website provided as a skeleton format for my testbench. I am still having trouble running my VHDL code with GHDL, so I have not been able to see the simulation yet. I will ask for help in class tomorrow.

[10 - 06 - 2021] I have fully installed the software Verilog 2019.1, and have started to work on practice exercises with the ZedBoard™ by Avnet Boards. ZedBoard™ is a complete development kit for designers interested in exploring designs using the Xilinx Zynq®-7000 All Programmable SoC. The board contains all the necessary interfaces and supporting functions to enable a wide range of applications.

[09 - 28 - 2021] I was able to install GHDL and have it work on my Mac laptop. I was able to use the line of code down below provided by BrewInstall.

[09 - 28 - 2021] Completed Assignment 1. I was able to find a VDHL Model that described how to set up a random number generator. I found the resource on this website: https://vhdlguide.readthedocs.io/en/latest/vhdl/dex.html

[09 - 27 - 2021] Today was my first day in the Quantum lab on the 6th floor of Buchard. For the rest of the semester, I will be working with a Zeboard, and programming in Verilog. I will be going in most days of the week in the morning to learn more about the project and help with current FPGA- related projects.

[09 - 16 - 2021] Read up to chapter 8 of the Free Range VHDL textbook so far for the class. Will need to spend some time looking over the rest of the chapters and reviewing more of the data types and how to declare them.