COFFE 2 - Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures

COFFE 2 is an open source tool to create the circuitry and area, delay and power models for FPGA tiles (logic, RAM or heterogeneous tiles like DSP blocks). It lets you evaluate your new FPGA architecture ideas quickly and with high accuracy.

COFFE 2 takes as input a description of the FPGA being modeled and automatically:

• Creates SPICE netlists for different components in the target FPGA.

• Sizes the transistors for the logic blocks, memory blocks, and routing resources.

• Synthesizes, places, and routes the core of heterogeneous blocks using an ASIC flow.

• Creates and sizes the components required to interface the heterogeneous blocks to the FPGA programmable routing.

COFFE can be used together with The Verilog to Routing (VTR) project to perform system-level exploration of FPGA architectures.