Created project using an PCIe root-complex and endpoint through the Programmable Logic (PL) on a Xilinx Artix-7. 

PCIe Root Complex is the Root of a hierarchy that connects with the CPU and Memory sub-systems. Other than the Root Complex, such as an end-point or a switch do not have the connection with CPU or Memory. All connections pass through Root Complex sub-system. It supports one or more PCIe ports.PCIe (Peripheral Component Interconnect Express) Root Complex is a central component in a computer system that manages communication between the CPU and peripheral devices connected through the PCIe interface. It acts as the interface between the CPU and the PCI Express fabric, which provides a high-speed data transfer between various components in the system. The Root Complex manages the transactions and data flow over the PCIe bus and ensures that the correct data is sent to the correct device.

VGA Interface using Altera DE1 Project - GitHub

Programmed a VGA Interface in Intel Quartus Prime using VHDL to output in synchronization with a custom programmed finite-state machine. A combined effort of all the knowledge learned from VLSI class consisting of a 4-but finite state machine (FSM) composed of 16 states (0 to 15) showing unique output display over VGA.

Each state will be shown on a computer monitor over VGA as well as on LEDs. Each state has a unique output that will be displayed on 4 8-segment displays that will be transitioned to after every second if an enable switch is on. A display switch is used to switch between the unique output or the current time and state number. This should be tested on an FPGA board (ex. Altera DE1 board) after appropriate pin assignments.

Intel Quartus Prime was used. View VLSI VGA Interface Design Project.docx for more details. 

Can upload to Quartus Prime (Quartus II Web Edition v9.1 sp2) might have been used) to make new video on physical FPGA to show the switches working as well.