Chris Keenan

I pledge on my honor that I have abided by the Stevens Honor System

My GitHub: https://github.com/ckeenan001

Weekly Progress

Week 1: Textbook (Free Range VHDL) downloaded
Week 2: Have to get GTK wave viewer, and VHDL software
Week 3: Vivado account set up and download process begins
- Issues arose with my account and installation. Professor Lu helped to fix these issues on Tuesday
Week 4: Vivado was downloaded and installed
Week 5: Lab 1, finding the correct board error was solved in class. Synthesis and Implementation ws run and completed. A new error in regards to the bit streaming and connection to the board has now appeared.
Week 6: Lab 1 completed
- Design

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;
ENTITY leddec IS PORT ( dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0); data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) );END leddec;
ARCHITECTURE Behavioral OF leddec ISBEGIN -- Turn on segments corresponding to 4-bit data word seg <= "0000001" WHEN data = "0000" ELSE --0 "1001111" WHEN data = "0001" ELSE --1 "0010010" WHEN data = "0010" ELSE --2 "0000110" WHEN data = "0011" ELSE --3 "1001100" WHEN data = "0100" ELSE --4 "0100100" WHEN data = "0101" ELSE --5 "0100000" WHEN data = "0110" ELSE --6 "0001111" WHEN data = "0111" ELSE --7 "0000000" WHEN data = "1000" ELSE --8 "0000100" WHEN data = "1001" ELSE --9 "0001000" WHEN data = "1010" ELSE --A "1100000" WHEN data = "1011" ELSE --B "0110001" WHEN data = "1100" ELSE --C "1000010" WHEN data = "1101" ELSE --D "0110000" WHEN data = "1110" ELSE --E "0111000" WHEN data = "1111" ELSE --F "1111111"; -- Turn on anode of 7-segment display addressed by 2-bit digit selector dig anode <= "1110" WHEN dig = "00" ELSE --0 "1101" WHEN dig = "01" ELSE --1 "1011" WHEN dig = "10" ELSE --2 "0111" WHEN dig = "11" ELSE --3 "1111";END Behavioral;

- Constraints

#FPGA I/O Pin Locations
set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {dig[0]}]set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {dig[1]}]
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {data[0]}]set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {data[1]}]set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {data[2]}]set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {data[3]}]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {seg[0]}]set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {seg[1]}]set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {seg[2]}]set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {seg[3]}]set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {seg[4]}]set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {seg[5]}]set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {seg[6]}]
set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {anode[0]}]set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {anode[1]}]set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {anode[2]}]set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {anode[3]}]

- Implementation and Synthesis

Week 7: Lab 2 Completed
- Design
  - Hexcount

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;
ENTITY hexcount IS PORT ( clk_100MHz : IN STD_LOGIC; anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) );END hexcount;
ARCHITECTURE Behavioral OF hexcount IS
COMPONENT counter IS PORT ( clk : IN STD_LOGIC; count : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); --NEED CHANGE! counter now output 16 bits for all 4 displays mpx : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) ); END COMPONENT;
COMPONENT leddec IS PORT ( dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0); data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); --DONT change, data is fixed 4 bits in leddec for each displays anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END COMPONENT;
SIGNAL S : STD_LOGIC_VECTOR (15 DOWNTO 0); -- connect C1 and L1 for values of 4 digits SIGNAL md : STD_LOGIC_VECTOR (1 DOWNTO 0); -- mpx selects displays SIGNAL display : STD_LOGIC_VECTOR (3 DOWNTO 0); -- send digit for only one display to leddec
BEGIN C1 : counter PORT MAP(clk => clk_100MHz, count => S, mpx => md); L1 : leddec PORT MAP(dig => md, data => display, anode => anode, seg => seg); --mpx --process(md) --begin -- if md = "00" then -- display <= S(3 downto 0); -- elsif md = "01" then -- display <= S(7 downto 4); -- elsif md = "10" then -- display <= S(11 downto 8); -- elsif md = "11" then -- display <= S(15 downto 12); -- end if; --end process;
display <= S(3 DOWNTO 0) WHEN md = "00" ELSE S(7 DOWNTO 4) WHEN md = "01" ELSE S(11 DOWNTO 8) WHEN md = "10" ELSE S(15 DOWNTO 12);
END Behavioral;

- - Counter

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter IS PORT ( clk : IN STD_LOGIC; count : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); --NEED REVISE! 16 bits mpx : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)); --NEW ONE ADD! send signal to select displaysEND counter;
ARCHITECTURE Behavioral OF counter IS SIGNAL cnt : STD_LOGIC_VECTOR (38 DOWNTO 0); -- 39 bit counterBEGIN PROCESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEN -- on rising edge of clock cnt <= cnt + 1; -- increment counter END IF; END PROCESS; count <= cnt (38 DOWNTO 23); -- 16bits mpx <= cnt (18 DOWNTO 17); -- 2bitsEND Behavioral;

- Constraints

#FPGA I/0 Locations
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk_100MHz]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {seg[0]}]set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {seg[1]}]set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {seg[2]}]set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {seg[3]}]set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {seg[4]}]set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {seg[5]}]set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {seg[6]}]
set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {anode[0]}]set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {anode[1]}]set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {anode[2]}]set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {anode[3]}]

- Synthesis and Implementation

Week 8: Lab 3 Bouncing Ball

Design
- Vga_top

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vga_top IS PORT ( clk_in : IN STD_LOGIC; vga_red : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); vga_green : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); vga_blue : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); vga_hsync : OUT STD_LOGIC; vga_vsync : OUT STD_LOGIC );END vga_top;
ARCHITECTURE Behavioral OF vga_top IS SIGNAL pxl_clk : STD_LOGIC; -- internal signals to connect modules SIGNAL S_red, S_green, S_blue : STD_LOGIC; SIGNAL S_vsync : STD_LOGIC; SIGNAL S_pixel_row, S_pixel_col : STD_LOGIC_VECTOR (10 DOWNTO 0); COMPONENT ball IS PORT ( v_sync : IN STD_LOGIC; pixel_row : IN STD_LOGIC_VECTOR(10 DOWNTO 0); pixel_col : IN STD_LOGIC_VECTOR(10 DOWNTO 0); red : OUT STD_LOGIC; green : OUT STD_LOGIC; blue : OUT STD_LOGIC ); END COMPONENT; COMPONENT vga_sync IS PORT ( pixel_clk : IN STD_LOGIC; red_in : IN STD_LOGIC; green_in : IN STD_LOGIC; blue_in : IN STD_LOGIC; red_out : OUT STD_LOGIC; green_out : OUT STD_LOGIC; blue_out : OUT STD_LOGIC; hsync : OUT STD_LOGIC; vsync : OUT STD_LOGIC; pixel_row : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); pixel_col : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) ); END COMPONENT; component clk_wiz_0 is port ( clk_in1 : in std_logic; clk_out1 : out std_logic ); end component; BEGIN -- vga_driver only drives MSB of red, green & blue -- so set other bits to zero vga_red(1 DOWNTO 0) <= "00"; vga_green(1 DOWNTO 0) <= "00"; vga_blue(0) <= '0';
add_ball : ball PORT MAP( --instantiate ball component v_sync => S_vsync, pixel_row => S_pixel_row, pixel_col => S_pixel_col, red => S_red, green => S_green, blue => S_blue );
vga_driver : vga_sync PORT MAP( --instantiate vga_sync component pixel_clk => pxl_clk, red_in => S_red, green_in => S_green, blue_in => S_blue, red_out => vga_red(2), green_out => vga_green(2), blue_out => vga_blue(1), pixel_row => S_pixel_row, pixel_col => S_pixel_col, hsync => vga_hsync, vsync => S_vsync ); vga_vsync <= S_vsync; --connect output vsync clk_wiz_0_inst : clk_wiz_0 port map ( clk_in1 => clk_in, clk_out1 => pxl_clk );

Ball

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ball IS PORT ( v_sync : IN STD_LOGIC; pixel_row : IN STD_LOGIC_VECTOR(10 DOWNTO 0); pixel_col : IN STD_LOGIC_VECTOR(10 DOWNTO 0); red : OUT STD_LOGIC; green : OUT STD_LOGIC; blue : OUT STD_LOGIC );END ball;
ARCHITECTURE Behavioral OF ball IS CONSTANT size : INTEGER := 8; SIGNAL ball_on : STD_LOGIC; -- indicates whether ball is over current pixel position -- current ball position - intitialized to center of screen SIGNAL ball_x : STD_LOGIC_VECTOR(10 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(400, 11); SIGNAL ball_y : STD_LOGIC_VECTOR(10 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(300, 11); -- current ball motion - initialized to +4 pixels/frame SIGNAL ball_y_motion : STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000100";BEGIN red <= '1'; -- color setup for red ball on white background green <= NOT ball_on; blue <= NOT ball_on; -- process to draw ball current pixel address is covered by ball position bdraw : PROCESS (ball_x, ball_y, pixel_row, pixel_col) IS BEGIN IF (pixel_col >= ball_x - size) AND (pixel_col <= ball_x + size) AND (pixel_row >= ball_y - size) AND (pixel_row <= ball_y + size) THEN ball_on <= '1'; ELSE ball_on <= '0'; END IF; END PROCESS; -- process to move ball once every frame (i.e. once every vsync pulse) mball : PROCESS BEGIN WAIT UNTIL rising_edge(v_sync); -- allow for bounce off top or bottom of screen IF ball_y + size >= 600 THEN ball_y_motion <= "11111111100"; -- -4 pixels ELSIF ball_y <= size THEN ball_y_motion <= "00000000100"; -- +4 pixels END IF; ball_y <= ball_y + ball_y_motion; -- compute next ball position END PROCESS;END Behavioral;

clk_wiz_0

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;use ieee.numeric_std.all;
library unisim;use unisim.vcomponents.all;
entity clk_wiz_0 isport (-- Clock in ports clk_in1 : in std_logic; -- Clock out ports clk_out1 : out std_logic );end clk_wiz_0;
architecture xilinx of clk_wiz_0 is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_wiz_0_clk_wizport (-- Clock in ports clk_in1 : in std_logic; -- Clock out ports clk_out1 : out std_logic );end component;begin
U0: clk_wiz_0_clk_wiz port map (
-- Clock in ports clk_in1 => clk_in1, -- Clock out ports clk_out1 => clk_out1

clk_wiz_0_wiz_clk

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;use ieee.numeric_std.all;
library unisim;use unisim.vcomponents.all;
entity clk_wiz_0_clk_wiz isport (-- Clock in ports clk_in1 : in std_logic; -- Clock out ports clk_out1 : out std_logic );end clk_wiz_0_clk_wiz;
architecture xilinx of clk_wiz_0_clk_wiz is -- Input clock buffering / unused connectors signal clk_in1_clk_wiz_0 : std_logic; -- Output clock buffering / unused connectors signal clkfbout_clk_wiz_0 : std_logic; signal clkfbout_buf_clk_wiz_0 : std_logic; signal clkfboutb_unused : std_logic; signal clk_out1_clk_wiz_0 : std_logic; signal clkout0b_unused : std_logic; signal clkout1_unused : std_logic; signal clkout1b_unused : std_logic; signal clkout2_unused : std_logic; signal clkout2b_unused : std_logic; signal clkout3_unused : std_logic; signal clkout3b_unused : std_logic; signal clkout4_unused : std_logic; signal clkout5_unused : std_logic; signal clkout6_unused : std_logic; -- Dynamic programming unused signals signal do_unused : std_logic_vector(15 downto 0); signal drdy_unused : std_logic; -- Dynamic phase shift unused signals signal psdone_unused : std_logic; signal locked_int : std_logic; -- Unused status signals signal clkfbstopped_unused : std_logic; signal clkinstopped_unused : std_logic;
begin

-- Input buffering --------------------------------------clk_in1_clk_wiz_0 <= clk_in1;

-- Clocking PRIMITIVE -------------------------------------- -- Instantiation of the MMCM PRIMITIVE -- * Unused inputs are tied off -- * Unused outputs are labeled unused mmcm_adv_inst : MMCME2_ADV generic map (BANDWIDTH => "OPTIMIZED", CLKOUT4_CASCADE => FALSE, COMPENSATION => "ZHOLD", STARTUP_WAIT => FALSE, DIVCLK_DIVIDE => 1, CLKFBOUT_MULT_F => 10.125, CLKFBOUT_PHASE => 0.000, CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_DIVIDE_F => 25.3125, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT0_USE_FINE_PS => FALSE, CLKIN1_PERIOD => 10.0, REF_JITTER1 => 0.010) port map -- Output clocks ( CLKFBOUT => clkfbout_clk_wiz_0, CLKFBOUTB => clkfboutb_unused, CLKOUT0 => clk_out1_clk_wiz_0, CLKOUT0B => clkout0b_unused, CLKOUT1 => clkout1_unused, CLKOUT1B => clkout1b_unused, CLKOUT2 => clkout2_unused, CLKOUT2B => clkout2b_unused, CLKOUT3 => clkout3_unused, CLKOUT3B => clkout3b_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, CLKOUT6 => clkout6_unused, -- Input clock control CLKFBIN => clkfbout_buf_clk_wiz_0, CLKIN1 => clk_in1_clk_wiz_0, CLKIN2 => '0', -- Tied to always select the primary input clock CLKINSEL => '1', -- Ports for dynamic reconfiguration DADDR => (others => '0'), DCLK => '0', DEN => '0', DI => (others => '0'), DO => do_unused, DRDY => drdy_unused, DWE => '0', -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => psdone_unused, -- Other control and status signals LOCKED => locked_int, CLKINSTOPPED => clkinstopped_unused, CLKFBSTOPPED => clkfbstopped_unused, PWRDWN => '0', RST => '0');

-- Output buffering -------------------------------------
clkf_buf : BUFG port map (O => clkfbout_buf_clk_wiz_0, I => clkfbout_clk_wiz_0);

clkout1_buf : BUFG port map (O => clk_out1, I => clk_out1_clk_wiz_0);

vga_sync

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vga_sync IS PORT ( pixel_clk : IN STD_LOGIC; red_in : IN STD_LOGIC; green_in : IN STD_LOGIC; blue_in : IN STD_LOGIC; red_out : OUT STD_LOGIC; green_out : OUT STD_LOGIC; blue_out : OUT STD_LOGIC; hsync : OUT STD_LOGIC; vsync : OUT STD_LOGIC; pixel_row : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); pixel_col : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) );END vga_sync;
ARCHITECTURE Behavioral OF vga_sync IS SIGNAL h_cnt, v_cnt : STD_LOGIC_VECTOR (10 DOWNTO 0);
CONSTANT H : INTEGER := 800; CONSTANT V : INTEGER := 600; CONSTANT H_FP : INTEGER := 40; CONSTANT H_BP : INTEGER := 88; CONSTANT H_SYNC : INTEGER := 128; CONSTANT V_FP : INTEGER := 1; CONSTANT V_BP : INTEGER := 23; CONSTANT V_SYNC : INTEGER := 4;
CONSTANT FREQ : INTEGER := 60;
BEGIN sync_pr : PROCESS VARIABLE video_on : STD_LOGIC; BEGIN WAIT UNTIL rising_edge(pixel_clk); -- Generate Horizontal Timing Signals for Video Signal -- total horizontal line width = H + H_FP + H_SYNC + H_BP -- Reset h_cnt when at end of line IF (h_cnt >= H + H_FP + H_SYNC + H_BP - 1) THEN h_cnt <= (others => '0'); ELSE h_cnt <= h_cnt + 1; END IF; -- Pull down hsync after front porch IF (h_cnt >= H + H_FP) AND (h_cnt <= H + H_FP + H_SYNC) THEN hsync <= '0'; ELSE hsync <= '1'; END IF;
IF (v_cnt >= V + V_FP + V_SYNC + V_BP - 1) AND (h_cnt = H + FREQ - 1) THEN v_cnt <= (others => '0'); ELSIF (h_cnt = H + FREQ - 1) THEN v_cnt <= v_cnt + 1; END IF; IF (v_cnt >= V + V_FP) AND (v_cnt <= V + V_FP + V_SYNC) THEN vsync <= '0'; ELSE vsync <= '1'; END IF; -- Generate Video Signals and Pixel Address IF (h_cnt < H) AND (v_cnt < V) THEN video_on := '1'; ELSE video_on := '0'; END IF; pixel_col <= h_cnt; pixel_row <= v_cnt; -- Register video to clock edge and suppress video during blanking and sync periods red_out <= red_in AND video_on; green_out <= green_in AND video_on; blue_out <= blue_in AND video_on; END PROCESS;END Behavioral;

Constraints

## Clock signalset_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_in }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhzcreate_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_in }];##VGA Connectorset_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_red[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_red[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_red[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_green[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_green[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_green[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_blue[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_blue[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hsync }]; #IO_L4P_T0_15 Sch=vga_hsset_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vsync }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs

Synthesis and Implementation

Week 9: Lab 4 Hex Counter

Design
- Keypad

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;
ENTITY keypad IS PORT ( samp_ck : IN STD_LOGIC; -- clock to strobe columns col : OUT STD_LOGIC_VECTOR (4 DOWNTO 1); -- output column lines row : IN STD_LOGIC_VECTOR (4 DOWNTO 1); -- input row lines value : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- hex value of key depressed hit : OUT STD_LOGIC); -- indicates when a key has been pressedEND keypad;
ARCHITECTURE Behavioral OF keypad IS SIGNAL CV1, CV2, CV3, CV4 : std_logic_vector (4 DOWNTO 1) := "1111"; -- column vector of each row SIGNAL curr_col : std_logic_vector (4 DOWNTO 1) := "1110"; -- current column codeBEGIN -- This process synchronously tests the state of the keypad buttons. On each edge of samp_ck, -- this module outputs a column code to the keypad in which one column line is held low while the -- other three column lines are held high. The row outputs of that column are then read -- into the corresponding column vector. The current column is then updated ready for the next -- clock edge. Remember that curr_col is not updated until the process suspends. strobe_proc : PROCESS BEGIN WAIT UNTIL rising_edge(samp_ck); CASE curr_col IS WHEN "1110" => CV1 <= row; curr_col <= "1101"; WHEN "1101" => CV2 <= row; curr_col <= "1011"; WHEN "1011" => CV3 <= row; curr_col <= "0111"; WHEN "0111" => CV4 <= row; curr_col <= "1110"; WHEN OTHERS => curr_col <= "1110"; END CASE; END PROCESS; -- This process runs whenever any of the column vectors change. Each vector is tested to see -- if there are any '0's in the vector. This would indicate that a button had been pushed in -- that column. If so, the value of the button is output and the hit signal is assereted. If -- not button is pushed, the hit signal is cleared out_proc : PROCESS (CV1, CV2, CV3, CV4) BEGIN hit <= '1'; IF CV1(1) = '0' THEN value <= X"1"; ELSIF CV1(2) = '0' THEN value <= X"4"; ELSIF CV1(3) = '0' THEN value <= X"7"; ELSIF CV1(4) = '0' THEN value <= X"0"; ELSIF CV2(1) = '0' THEN value <= X"2"; ELSIF CV2(2) = '0' THEN value <= X"5"; ELSIF CV2(3) = '0' THEN value <= X"8"; ELSIF CV2(4) = '0' THEN value <= X"F"; ELSIF CV3(1) = '0' THEN value <= X"3"; ELSIF CV3(2) = '0' THEN value <= X"6"; ELSIF CV3(3) = '0' THEN value <= X"9"; ELSIF CV3(4) = '0' THEN value <= X"E"; ELSIF CV4(1) = '0' THEN value <= X"A"; ELSIF CV4(2) = '0' THEN value <= X"B"; ELSIF CV4(3) = '0' THEN value <= X"C"; ELSIF CV4(4) = '0' THEN value <= X"D"; ELSE hit <= '0'; value <= X"0"; END IF; END PROCESS; col <= curr_col;END Behavioral;

Leddec16

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;
ENTITY leddec16 IS PORT ( dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- which digit to currently display data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- 16-bit (4-digit) data anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- which anode to turn on seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- segment code for current digitEND leddec16;
ARCHITECTURE Behavioral OF leddec16 IS SIGNAL data4 : STD_LOGIC_VECTOR (3 DOWNTO 0); -- binary value of current digitBEGIN -- Select digit data to be displayed in this mpx period data4 <= data(3 DOWNTO 0) WHEN dig = "00" ELSE --digit 0 data(7 DOWNTO 4) WHEN dig = "01" ELSE --digit 1 data(11 DOWNTO 8) WHEN dig = "10" ELSE --digit 2 data(15 DOWNTO 12); --digit 3 -- Turn on segments corresponding to 4-bit data word seg <= "0000001" WHEN data4 = "0000" ELSE --0 "1001111" WHEN data4 = "0001" ELSE --1 "0010010" WHEN data4 = "0010" ELSE --2 "0000110" WHEN data4 = "0011" ELSE --3 "1001100" WHEN data4 = "0100" ELSE --4 "0100100" WHEN data4 = "0101" ELSE --5 "0100000" WHEN data4 = "0110" ELSE --6 "0001111" WHEN data4 = "0111" ELSE --7 "0000000" WHEN data4 = "1000" ELSE --8 "0000100" WHEN data4 = "1001" ELSE --9 "0001000" WHEN data4 = "1010" ELSE --A "1100000" WHEN data4 = "1011" ELSE --B "0110001" WHEN data4 = "1100" ELSE --C "1000010" WHEN data4 = "1101" ELSE --D "0110000" WHEN data4 = "1110" ELSE --E "0111000" WHEN data4 = "1111" ELSE --F "1111111"; -- Turn on anode of 7-segment display addressed by 2-bit digit selector dig anode <= "1110" WHEN dig = "00" ELSE -- digit 0 "1101" WHEN dig = "01" ELSE -- digit 1 "1011" WHEN dig = "10" ELSE -- digit 2 "0111" WHEN dig = "11" ELSE -- digit 3 "1111";END Behavioral;

Hexcalc

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY hexcalc IS PORT ( clk_50MHz : IN STD_LOGIC; -- system clock (50 MHz) SEG7_anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- anodes of four 7-seg displays SEG7_seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); -- common segments of 7-seg displays bt_clr : IN STD_LOGIC; -- calculator "clear" button bt_plus : IN STD_LOGIC; -- calculator "+" button bt_eq : IN STD_LOGIC; -- calculator "-" button KB_col : OUT STD_LOGIC_VECTOR (4 DOWNTO 1); -- keypad column pins KB_row : IN STD_LOGIC_VECTOR (4 DOWNTO 1)); -- keypad row pinsEND hexcalc;
ARCHITECTURE Behavioral OF hexcalc IS COMPONENT keypad IS PORT ( samp_ck : IN STD_LOGIC; col : OUT STD_LOGIC_VECTOR (4 DOWNTO 1); row : IN STD_LOGIC_VECTOR (4 DOWNTO 1); value : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); hit : OUT STD_LOGIC ); END COMPONENT; COMPONENT leddec16 IS PORT ( dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0); data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END COMPONENT; SIGNAL cnt : std_logic_vector(20 DOWNTO 0); -- counter to generate timing signals SIGNAL kp_clk, kp_hit, sm_clk : std_logic; SIGNAL kp_value : std_logic_vector (3 DOWNTO 0); SIGNAL nx_acc, acc : std_logic_vector (15 DOWNTO 0); -- accumulated sum SIGNAL nx_operand, operand : std_logic_vector (15 DOWNTO 0); -- operand SIGNAL display : std_logic_vector (15 DOWNTO 0); -- value to be displayed SIGNAL led_mpx : STD_LOGIC_VECTOR (1 DOWNTO 0); -- 7-seg multiplexing clock TYPE state IS (ENTER_ACC, ACC_RELEASE, START_OP, OP_RELEASE, ENTER_OP, SHOW_RESULT); -- state machine states SIGNAL pr_state, nx_state : state; -- present and next statesBEGIN ck_proc : PROCESS (clk_50MHz) BEGIN IF rising_edge(clk_50MHz) THEN -- on rising edge of clock cnt <= cnt + 1; -- increment counter END IF; END PROCESS; kp_clk <= cnt(15); -- keypad interrogation clock sm_clk <= cnt(20); -- state machine clock led_mpx <= cnt(18 DOWNTO 17); -- 7-seg multiplexing clock kp1 : keypad PORT MAP( samp_ck => kp_clk, col => KB_col, row => KB_row, value => kp_value, hit => kp_hit ); led1 : leddec16 PORT MAP( dig => led_mpx, data => display, anode => SEG7_anode, seg => SEG7_seg ); sm_ck_pr : PROCESS (bt_clr, sm_clk) -- state machine clock process BEGIN IF bt_clr = '1' THEN -- reset to known state acc <= X"0000"; operand <= X"0000"; pr_state <= ENTER_ACC; ELSIF rising_edge (sm_clk) THEN -- on rising clock edge pr_state <= nx_state; -- update present state acc <= nx_acc; -- update accumulator operand <= nx_operand; -- update operand END IF; END PROCESS; -- state maching combinatorial process -- determines output of state machine and next state sm_comb_pr : PROCESS (kp_hit, kp_value, bt_plus, bt_eq, acc, operand, pr_state) BEGIN nx_acc <= acc; -- default values of nx_acc, nx_operand & display nx_operand <= operand; display <= acc; CASE pr_state IS -- depending on present state... WHEN ENTER_ACC => -- waiting for next digit in 1st operand entry IF kp_hit = '1' THEN nx_acc <= acc(11 DOWNTO 0) & kp_value; nx_state <= ACC_RELEASE; ELSIF bt_plus = '1' THEN nx_state <= START_OP; ELSE nx_state <= ENTER_ACC; END IF; WHEN ACC_RELEASE => -- waiting for button to be released IF kp_hit = '0' THEN nx_state <= ENTER_ACC; ELSE nx_state <= ACC_RELEASE; END IF; WHEN START_OP => -- ready to start entering 2nd operand IF kp_hit = '1' THEN nx_operand <= X"000" & kp_value; nx_state <= OP_RELEASE; display <= operand; ELSE nx_state <= START_OP; END IF; WHEN OP_RELEASE => -- waiting for button ot be released display <= operand; IF kp_hit = '0' THEN nx_state <= ENTER_OP; ELSE nx_state <= OP_RELEASE; END IF; WHEN ENTER_OP => -- waiting for next digit in 2nd operand display <= operand; IF bt_eq = '1' THEN nx_acc <= acc + operand; nx_state <= SHOW_RESULT; ELSIF kp_hit = '1' THEN nx_operand <= operand(11 DOWNTO 0) & kp_value; nx_state <= OP_RELEASE; ELSE nx_state <= ENTER_OP; END IF; WHEN SHOW_RESULT => -- display result of addition IF kp_hit = '1' THEN nx_acc <= X"000" & kp_value; nx_state <= ACC_RELEASE; ELSE nx_state <= SHOW_RESULT; END IF; END CASE; END PROCESS;END Behavioral;

Constraints

set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_50MHz }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhzcreate_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_50MHz}];
##Buttons
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { bt_clr }]; #IO_L9P_T1_DQS_14 Sch=btncset_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { bt_plus }]; #IO_L4N_T0_D05_14 Sch=btnuset_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { bt_eq }]; #IO_L12P_T1_MRCC_14 Sch=btnl#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
##Pmod Header JA
set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { KB_col[4] }]; #IO_L20N_T3_A19_15 Sch=ja[1]set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { KB_col[3] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { KB_col[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { KB_col[1] }]; #IO_L18N_T2_A23_15 Sch=ja[4]set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { KB_row[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7]set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { KB_row[3] }]; #IO_L16P_T2_A28_15 Sch=ja[8]set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { KB_row[2] }]; #IO_L22N_T3_A16_15 Sch=ja[9]set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { KB_row[1] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
##7-Segment Displayset_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[0]}]set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[1]}]set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[2]}]set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[3]}]set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[4]}]set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[5]}]set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {SEG7_seg[6]}]
set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[0]}]set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[1]}]set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[2]}]set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {SEG7_anode[3]}]

Week 10: Lab 5 Siren

Design
- Dac_if

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;
ENTITY dac_if IS PORT ( SCLK : IN STD_LOGIC; -- serial clock (1.56 MHz) L_start : IN STD_LOGIC; -- strobe to load LEFT data R_start : IN STD_LOGIC; -- strobe to load RIGHT data L_data : IN SIGNED (15 DOWNTO 0); -- LEFT data (15-bit signed) R_data : IN SIGNED (15 DOWNTO 0); -- RIGHT data (15-bit signed) SDATA : OUT STD_LOGIC); -- serial data stream to DACEND dac_if;
ARCHITECTURE Behavioral OF dac_if IS SIGNAL sreg : STD_LOGIC_VECTOR (15 DOWNTO 0); -- 16-bit shift register to do -- parallel to serial conversionBEGIN -- SREG is used to serially shift data out to DAC, MSBit first. -- Left data is loaded into SREG on falling edge of SCLK when L_start is active. -- Right data is loaded into SREG on falling edge of SCLK when R_start is active. -- At other times, falling edge of SCLK causes REG to logically shift one bit left -- Serial data to DAC is MSBit of SREG dac_proc : PROCESS BEGIN WAIT UNTIL falling_edge(SCLK); IF L_start = '1' THEN sreg <= std_logic_vector (L_data); -- load LEFT data into SREG ELSIF R_start = '1' THEN sreg <= std_logic_vector (R_data); -- load RIGHT data into SREG ELSE sreg <= sreg(14 DOWNTO 0) & '0'; -- logically shift SREG one bit left END IF; END PROCESS; SDATA <= sreg(15); -- serial data to DAC is MSBit of SREGEND Behavioral;

Siren

library IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;
ENTITY siren IS PORT ( clk_50MHz : IN STD_LOGIC; -- system clock (50 MHz) dac_MCLK : OUT STD_LOGIC; -- outputs to PMODI2L DAC dac_LRCK : OUT STD_LOGIC; dac_SCLK : OUT STD_LOGIC; dac_SDIN : OUT STD_LOGIC );END siren;
ARCHITECTURE Behavioral OF siren IS CONSTANT lo_tone : UNSIGNED (13 DOWNTO 0) := to_unsigned (344, 14); -- lower limit of siren = 256 Hz CONSTANT hi_tone : UNSIGNED (13 DOWNTO 0) := to_unsigned (687, 14); -- upper limit of siren = 512 Hz CONSTANT wail_speed : UNSIGNED (7 DOWNTO 0) := to_unsigned (8, 8); -- sets wailing speed COMPONENT dac_if IS PORT ( SCLK : IN STD_LOGIC; L_start : IN STD_LOGIC; R_start : IN STD_LOGIC; L_data : IN signed (15 DOWNTO 0); R_data : IN signed (15 DOWNTO 0); SDATA : OUT STD_LOGIC ); END COMPONENT; COMPONENT wail IS PORT ( lo_pitch : IN UNSIGNED (13 DOWNTO 0); hi_pitch : IN UNSIGNED (13 DOWNTO 0); wspeed : IN UNSIGNED (7 DOWNTO 0); wclk : IN STD_LOGIC; audio_clk : IN STD_LOGIC; audio_data : OUT SIGNED (15 DOWNTO 0) ); END COMPONENT; SIGNAL tcount : unsigned (19 DOWNTO 0) := (OTHERS => '0'); -- timing counter SIGNAL data_L, data_R : SIGNED (15 DOWNTO 0); -- 16-bit signed audio data SIGNAL dac_load_L, dac_load_R : STD_LOGIC; -- timing pulses to load DAC shift reg. SIGNAL slo_clk, sclk, audio_CLK : STD_LOGIC;BEGIN -- this process sets up a 20 bit binary counter clocked at 50MHz. This is used -- to generate all necessary timing signals. dac_load_L and dac_load_R are pulses -- sent to dac_if to load parallel data into shift register for serial clocking -- out to DAC tim_pr : PROCESS BEGIN WAIT UNTIL rising_edge(clk_50MHz); IF (tcount(9 DOWNTO 0) >= X"00F") AND (tcount(9 DOWNTO 0) < X"02E") THEN dac_load_L <= '1'; ELSE dac_load_L <= '0'; END IF; IF (tcount(9 DOWNTO 0) >= X"20F") AND (tcount(9 DOWNTO 0) < X"22E") THEN dac_load_R <= '1'; ELSE dac_load_R <= '0'; END IF; tcount <= tcount + 1; END PROCESS; dac_MCLK <= NOT tcount(1); -- DAC master clock (12.5 MHz) audio_CLK <= tcount(9); -- audio sampling rate (48.8 kHz) dac_LRCK <= audio_CLK; -- also sent to DAC as left/right clock sclk <= tcount(4); -- serial data clock (1.56 MHz) dac_SCLK <= sclk; -- also sent to DAC as SCLK slo_clk <= tcount(19); -- clock to control wailing of tone (47.6 Hz) dac : dac_if PORT MAP( SCLK => sclk, -- instantiate parallel to serial DAC interface L_start => dac_load_L, R_start => dac_load_R, L_data => data_L, R_data => data_R, SDATA => dac_SDIN ); w1 : wail PORT MAP( lo_pitch => lo_tone, -- instantiate wailing siren hi_pitch => hi_tone, wspeed => wail_speed, wclk => slo_clk, audio_clk => audio_clk, audio_data => data_L ); data_R <= data_L; -- duplicate data on right channelEND Behavioral;

Tone

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;
-- Generates a 16-bit signed triangle wave sequence at a sampling rate determined-- by input clk and with a frequency of (clk*pitch)/65,536ENTITY tone IS PORT ( clk : IN STD_LOGIC; -- 48.8 kHz audio sampling clock pitch : IN UNSIGNED (13 DOWNTO 0); -- frequency (in units of 0.745 Hz) data : OUT SIGNED (15 DOWNTO 0)); -- signed triangle wave outEND tone;
ARCHITECTURE Behavioral OF tone IS SIGNAL count : unsigned (15 DOWNTO 0); -- represents current phase of waveform SIGNAL quad : std_logic_vector (1 DOWNTO 0); -- current quadrant of phase SIGNAL index : signed (15 DOWNTO 0); -- index into current quadrantBEGIN -- This process adds "pitch" to the current phase every sampling period. Generates -- an unsigned 16-bit sawtooth waveform. Frequency is determined by pitch. For -- example when pitch=1, then frequency will be 0.745 Hz. When pitch=16,384, frequency -- will be 12.2 kHz. cnt_pr : PROCESS BEGIN WAIT UNTIL rising_edge(clk); count <= count + pitch; END PROCESS; quad <= std_logic_vector (count (15 DOWNTO 14)); -- splits count range into 4 phases index <= signed ("00" & count (13 DOWNTO 0)); -- 14-bit index into the current phase -- This select statement converts an unsigned 16-bit sawtooth that ranges from 65,535 -- into a signed 12-bit triangle wave that ranges from -16,383 to +16,383 WITH quad SELECT data <= index WHEN "00", -- 1st quadrant 16383 - index WHEN "01", -- 2nd quadrant 0 - index WHEN "10", -- 3rd quadrant index - 16383 WHEN OTHERS; -- 4th quadrantEND Behavioral;

Wail

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;
-- Generates a "wailing siren" sound by instancing a "tone" module and modulating-- the pitch of the tone. The pitch is increased until it reaches hi_pitch and then-- decreased until it reaches lo_pitch and then increased again...etc.ENTITY wail IS PORT ( lo_pitch : IN UNSIGNED (13 DOWNTO 0); -- lowest pitch (in units of 0.745 Hz) hi_pitch : IN UNSIGNED (13 DOWNTO 0); -- highest pitch (in units of 0.745 Hz) wspeed : IN UNSIGNED (7 DOWNTO 0); -- speed of wail in pitch units/wclk wclk : IN STD_LOGIC; -- wailing clock (47.6 Hz) audio_clk : IN STD_LOGIC; -- audio sampling clock (48.8 kHz) audio_data : OUT SIGNED (15 DOWNTO 0)); -- output audio sequence (wailing tone)END wail;
ARCHITECTURE Behavioral OF wail IS COMPONENT tone IS PORT ( clk : IN STD_LOGIC; pitch : IN UNSIGNED (13 DOWNTO 0); data : OUT SIGNED (15 DOWNTO 0) ); END COMPONENT; SIGNAL curr_pitch : UNSIGNED (13 DOWNTO 0); -- current wailing pitchBEGIN -- this process modulates the current pitch. It keep a variable updn to indicate -- whether tome is currently rising or falling. Each wclk period it increments -- (or decrements) the current pitch by wspeed. When it reaches hi_pitch, it -- starts counting down. When it reaches lo_pitch, it starts counting up wp : PROCESS VARIABLE updn : std_logic; BEGIN WAIT UNTIL rising_edge(wclk); IF curr_pitch >= hi_pitch THEN updn := '0'; -- check to see if still in range ELSIF curr_pitch <= lo_pitch THEN updn := '1'; -- if not, adjust updn END IF; IF updn = '1' THEN curr_pitch <= curr_pitch + wspeed; -- modulate pitch according to ELSE curr_pitch <= curr_pitch - wspeed; -- current value of updn END IF; END PROCESS; tgen : tone PORT MAP( clk => audio_clk, -- instance a tone module pitch => curr_pitch, -- use curr-pitch to modulate tone data => audio_data );END Behavioral;

Constraints

create_clock -name clk_50MHz -period 20.00 [get_ports clk_50MHz]
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports clk_50MHz]
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { dac_LRCK }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { dac_SCLK }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { dac_SDIN }]; #IO_L18N_T2_A23_15 Sch=ja[4]
set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { dac_MCLK }]; #IO_L20N_T3_A19_15 Sch=ja[1]

Synthesis and Implementation

Week 11: Lab 6 Pong

Design
- Pong

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pong IS PORT ( clk_in : IN STD_LOGIC; -- system clock VGA_red : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- VGA outputs VGA_green : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); VGA_blue : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); VGA_hsync : OUT STD_LOGIC; VGA_vsync : OUT STD_LOGIC; ADC_CS : OUT STD_LOGIC; -- ADC signals ADC_SCLK : OUT STD_LOGIC; ADC_SDATA1 : IN STD_LOGIC; ADC_SDATA2 : IN STD_LOGIC; btn0 : IN STD_LOGIC); -- button to initiate serveEND pong;
ARCHITECTURE Behavioral OF pong IS SIGNAL pxl_clk : STD_LOGIC := '0'; -- 25 MHz clock to VGA sync module -- internal signals to connect modules SIGNAL S_red, S_green, S_blue : STD_LOGIC; --_VECTOR (3 DOWNTO 0); SIGNAL S_vsync : STD_LOGIC; SIGNAL S_pixel_row, S_pixel_col : STD_LOGIC_VECTOR (10 DOWNTO 0); SIGNAL batpos : STD_LOGIC_VECTOR (10 DOWNTO 0); -- 9 downto 0 SIGNAL serial_clk, sample_clk : STD_LOGIC; SIGNAL adout : STD_LOGIC_VECTOR (11 DOWNTO 0); SIGNAL count : STD_LOGIC_VECTOR (9 DOWNTO 0); -- counter to generate ADC clocks COMPONENT adc_if IS PORT ( SCK : IN STD_LOGIC; SDATA1 : IN STD_LOGIC; SDATA2 : IN STD_LOGIC; CS : IN STD_LOGIC; data_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); data_2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT; COMPONENT bat_n_ball IS PORT ( v_sync : IN STD_LOGIC; pixel_row : IN STD_LOGIC_VECTOR(10 DOWNTO 0); pixel_col : IN STD_LOGIC_VECTOR(10 DOWNTO 0); bat_x : IN STD_LOGIC_VECTOR (10 DOWNTO 0); serve : IN STD_LOGIC; red : OUT STD_LOGIC; green : OUT STD_LOGIC; blue : OUT STD_LOGIC ); END COMPONENT; COMPONENT vga_sync IS PORT ( pixel_clk : IN STD_LOGIC; red_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); green_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); blue_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); red_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); green_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); blue_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); hsync : OUT STD_LOGIC; vsync : OUT STD_LOGIC; pixel_row : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); pixel_col : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) ); END COMPONENT;
component clk_wiz_0 is port ( clk_in1 : in std_logic; clk_out1 : out std_logic ); end component; BEGIN -- Process to generate clock signals ckp : PROCESS BEGIN WAIT UNTIL rising_edge(clk_in); count <= count + 1; -- counter to generate ADC timing signals END PROCESS; serial_clk <= NOT count(4); -- 1.5 MHz serial clock for ADC ADC_SCLK <= serial_clk; sample_clk <= count(9); -- sampling clock is low for 16 SCLKs ADC_CS <= sample_clk; -- Multiplies ADC output (0-4095) by 5/32 to give bat position (0-640) --batpos <= ('0' & adout(11 DOWNTO 3)) + adout(11 DOWNTO 5); batpos <= ("00" & adout(11 DOWNTO 3)) + adout(11 DOWNTO 4); -- 512 + 256 = 768 adc : adc_if PORT MAP(-- instantiate ADC serial to parallel interface SCK => serial_clk, CS => sample_clk, SDATA1 => ADC_SDATA1, SDATA2 => ADC_SDATA2, data_1 => OPEN, data_2 => adout ); add_bb : bat_n_ball PORT MAP(--instantiate bat and ball component v_sync => S_vsync, pixel_row => S_pixel_row, pixel_col => S_pixel_col, bat_x => batpos, serve => btn0, red => S_red, green => S_green, blue => S_blue ); vga_driver : vga_sync PORT MAP(--instantiate vga_sync component pixel_clk => pxl_clk, red_in => S_red & "000", green_in => S_green & "000", blue_in => S_blue & "000", red_out => VGA_red, green_out => VGA_green, blue_out => VGA_blue, pixel_row => S_pixel_row, pixel_col => S_pixel_col, hsync => VGA_hsync, vsync => S_vsync ); VGA_vsync <= S_vsync; --connect output vsync clk_wiz_0_inst : clk_wiz_0 port map ( clk_in1 => clk_in, clk_out1 => pxl_clk );END Behavioral;

adc_if

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adc_if IS PORT ( SCK : IN STD_LOGIC; -- serial clock that goes to ADC SDATA1 : IN STD_LOGIC; -- serial data channel 1 SDATA2 : IN STD_LOGIC; -- serial data channel 2 CS : IN STD_LOGIC; -- chip select that initiates A/D conversion data_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); -- parallel 12-bit data ch1 data_2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); -- parallel 12-bit data ch2END adc_if;
ARCHITECTURE Behavioral OF adc_if IS SIGNAL pdata1, pdata2 : std_logic_vector (11 DOWNTO 0); -- 12-bit shift registersBEGIN -- this process waits for CS=0 and then clocks serial data from ADC into shift register -- MSBit first. After 16 SCK's, four leading zeros will have fallen out of the most significant -- end of the shift register and the register will contain the parallel12-bit data adpr : PROCESS BEGIN WAIT UNTIL falling_edge (SCK); IF CS = '0' THEN pdata1 <= pdata1 (10 DOWNTO 0) & SDATA1; pdata2 <= pdata2 (10 DOWNTO 0) & SDATA2; END IF; END PROCESS; -- this process waits for rising edge of CS and then loads parallel data -- from shift register into appropriate output port sync : PROCESS BEGIN WAIT UNTIL rising_edge (CS); data_1 <= pdata1; data_2 <= pdata2; END PROCESS;END Behavioral;

bat_n_ball

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY bat_n_ball IS PORT ( v_sync : IN STD_LOGIC; pixel_row : IN STD_LOGIC_VECTOR(10 DOWNTO 0); pixel_col : IN STD_LOGIC_VECTOR(10 DOWNTO 0); bat_x : IN STD_LOGIC_VECTOR (10 DOWNTO 0); -- current bat x position serve : IN STD_LOGIC; -- initiates serve red : OUT STD_LOGIC; green : OUT STD_LOGIC; blue : OUT STD_LOGIC );END bat_n_ball;
ARCHITECTURE Behavioral OF bat_n_ball IS CONSTANT bsize : INTEGER := 8; -- ball size in pixels CONSTANT bat_w : INTEGER := 20; -- bat width in pixels CONSTANT bat_h : INTEGER := 3; -- bat height in pixels -- distance ball moves each frame CONSTANT ball_speed : STD_LOGIC_VECTOR (10 DOWNTO 0) := CONV_STD_LOGIC_VECTOR (6, 11); SIGNAL ball_on : STD_LOGIC; -- indicates whether ball is at current pixel position SIGNAL bat_on : STD_LOGIC; -- indicates whether bat at over current pixel position SIGNAL game_on : STD_LOGIC := '0'; -- indicates whether ball is in play -- current ball position - intitialized to center of screen SIGNAL ball_x : STD_LOGIC_VECTOR(10 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(400, 11); SIGNAL ball_y : STD_LOGIC_VECTOR(10 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(300, 11); -- bat vertical position CONSTANT bat_y : STD_LOGIC_VECTOR(10 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(500, 11); -- current ball motion - initialized to (+ ball_speed) pixels/frame in both X and Y directions SIGNAL ball_x_motion, ball_y_motion : STD_LOGIC_VECTOR(10 DOWNTO 0) := ball_speed;BEGIN red <= NOT bat_on; -- color setup for red ball and cyan bat on white background green <= NOT ball_on; blue <= NOT ball_on; -- process to draw round ball -- set ball_on if current pixel address is covered by ball position balldraw : PROCESS (ball_x, ball_y, pixel_row, pixel_col) IS VARIABLE vx, vy : STD_LOGIC_VECTOR (10 DOWNTO 0); -- 9 downto 0 BEGIN IF pixel_col <= ball_x THEN -- vx = |ball_x - pixel_col| vx := ball_x - pixel_col; ELSE vx := pixel_col - ball_x; END IF; IF pixel_row <= ball_y THEN -- vy = |ball_y - pixel_row| vy := ball_y - pixel_row; ELSE vy := pixel_row - ball_y; END IF; IF ((vx * vx) + (vy * vy)) < (bsize * bsize) THEN -- test if radial distance < bsize ball_on <= game_on; ELSE ball_on <= '0'; END IF; END PROCESS; -- process to draw bat -- set bat_on if current pixel address is covered by bat position batdraw : PROCESS (bat_x, pixel_row, pixel_col) IS VARIABLE vx, vy : STD_LOGIC_VECTOR (10 DOWNTO 0); -- 9 downto 0 BEGIN IF ((pixel_col >= bat_x - bat_w) OR (bat_x <= bat_w)) AND pixel_col <= bat_x + bat_w AND pixel_row >= bat_y - bat_h AND pixel_row <= bat_y + bat_h THEN bat_on <= '1'; ELSE bat_on <= '0'; END IF; END PROCESS; -- process to move ball once every frame (i.e. once every vsync pulse) mball : PROCESS VARIABLE temp : STD_LOGIC_VECTOR (11 DOWNTO 0); BEGIN WAIT UNTIL rising_edge(v_sync); IF serve = '1' AND game_on = '0' THEN -- test for new serve game_on <= '1'; ball_y_motion <= (NOT ball_speed) + 1; -- set vspeed to (- ball_speed) pixels ELSIF ball_y <= bsize THEN -- bounce off top wall ball_y_motion <= ball_speed; -- set vspeed to (+ ball_speed) pixels ELSIF ball_y + bsize >= 600 THEN -- if ball meets bottom wall ball_y_motion <= (NOT ball_speed) + 1; -- set vspeed to (- ball_speed) pixels game_on <= '0'; -- and make ball disappear END IF; -- allow for bounce off left or right of screen IF ball_x + bsize >= 800 THEN -- bounce off right wall ball_x_motion <= (NOT ball_speed) + 1; -- set hspeed to (- ball_speed) pixels ELSIF ball_x <= bsize THEN -- bounce off left wall ball_x_motion <= ball_speed; -- set hspeed to (+ ball_speed) pixels END IF; -- allow for bounce off bat IF (ball_x + bsize/2) >= (bat_x - bat_w) AND (ball_x - bsize/2) <= (bat_x + bat_w) AND (ball_y + bsize/2) >= (bat_y - bat_h) AND (ball_y - bsize/2) <= (bat_y + bat_h) THEN ball_y_motion <= (NOT ball_speed) + 1; -- set vspeed to (- ball_speed) pixels END IF; -- compute next ball vertical position -- variable temp adds one more bit to calculation to fix unsigned underflow problems -- when ball_y is close to zero and ball_y_motion is negative temp := ('0' & ball_y) + (ball_y_motion(10) & ball_y_motion); IF game_on = '0' THEN ball_y <= CONV_STD_LOGIC_VECTOR(440, 11); ELSIF temp(11) = '1' THEN ball_y <= (OTHERS => '0'); ELSE ball_y <= temp(10 DOWNTO 0); -- 9 downto 0 END IF; -- compute next ball horizontal position -- variable temp adds one more bit to calculation to fix unsigned underflow problems -- when ball_x is close to zero and ball_x_motion is negative temp := ('0' & ball_x) + (ball_x_motion(10) & ball_x_motion); IF temp(11) = '1' THEN ball_x <= (OTHERS => '0'); ELSE ball_x <= temp(10 DOWNTO 0); END IF; END PROCESS;END Behavioral;

Vga_sync

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vga_sync IS PORT ( pixel_clk : IN STD_LOGIC; red_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); green_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); blue_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); red_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); green_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); blue_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); hsync : OUT STD_LOGIC; vsync : OUT STD_LOGIC; pixel_row : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); pixel_col : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) );END vga_sync;
ARCHITECTURE Behavioral OF vga_sync IS SIGNAL h_cnt, v_cnt : STD_LOGIC_VECTOR (10 DOWNTO 0);
CONSTANT H : INTEGER := 800; CONSTANT V : INTEGER := 600; CONSTANT H_FP : INTEGER := 40; CONSTANT H_BP : INTEGER := 88; CONSTANT H_SYNC : INTEGER := 128; CONSTANT V_FP : INTEGER := 1; CONSTANT V_BP : INTEGER := 23; CONSTANT V_SYNC : INTEGER := 4;
CONSTANT FREQ : INTEGER := 60;
BEGIN sync_pr : PROCESS VARIABLE video_on : STD_LOGIC; BEGIN WAIT UNTIL rising_edge(pixel_clk); -- Generate Horizontal Timing Signals for Video Signal -- total horizontal line width = H + H_FP + H_SYNC + H_BP -- Reset h_cnt when at end of line IF (h_cnt >= H + H_FP + H_SYNC + H_BP - 1) THEN h_cnt <= (others => '0'); ELSE h_cnt <= h_cnt + 1; END IF; -- Pull down hsync after front porch IF (h_cnt >= H + H_FP) AND (h_cnt <= H + H_FP + H_SYNC) THEN hsync <= '0'; ELSE hsync <= '1'; END IF;
IF (v_cnt >= V + V_FP + V_SYNC + V_BP - 1) AND (h_cnt = H + FREQ - 1) THEN v_cnt <= (others => '0'); ELSIF (h_cnt = H + FREQ - 1) THEN v_cnt <= v_cnt + 1; END IF; IF (v_cnt >= V + V_FP) AND (v_cnt <= V + V_FP + V_SYNC) THEN vsync <= '0'; ELSE vsync <= '1'; END IF; -- Generate Video Signals and Pixel Address IF (h_cnt < H) AND (v_cnt < V) THEN video_on := '1'; ELSE video_on := '0'; END IF; pixel_col <= h_cnt; pixel_row <= v_cnt; -- Register video to clock edge and suppress video during blanking and sync periods if video_on = '1' then red_out <= red_in; green_out <= green_in; blue_out <= blue_in; else red_out <= "0000"; green_out <= "0000"; blue_out <= "0000"; end if; END PROCESS;END Behavioral;

clk_wiz_0

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;use ieee.numeric_std.all;
library unisim;use unisim.vcomponents.all;
entity clk_wiz_0 isport (-- Clock in ports clk_in1 : in std_logic; -- Clock out ports clk_out1 : out std_logic );end clk_wiz_0;
architecture xilinx of clk_wiz_0 is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_wiz_0_clk_wizport (-- Clock in ports clk_in1 : in std_logic; -- Clock out ports clk_out1 : out std_logic );end component;
begin
U0: clk_wiz_0_clk_wiz port map (
-- Clock in ports clk_in1 => clk_in1, -- Clock out ports clk_out1 => clk_out1 );
end xilinx;

clk_wiz_0_wiz_clk

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;use ieee.numeric_std.all;
library unisim;use unisim.vcomponents.all;
entity clk_wiz_0_clk_wiz isport (-- Clock in ports clk_in1 : in std_logic; -- Clock out ports clk_out1 : out std_logic );end clk_wiz_0_clk_wiz;
architecture xilinx of clk_wiz_0_clk_wiz is -- Input clock buffering / unused connectors signal clk_in1_clk_wiz_0 : std_logic; -- Output clock buffering / unused connectors signal clkfbout_clk_wiz_0 : std_logic; signal clkfbout_buf_clk_wiz_0 : std_logic; signal clkfboutb_unused : std_logic; signal clk_out1_clk_wiz_0 : std_logic; signal clkout0b_unused : std_logic; signal clkout1_unused : std_logic; signal clkout1b_unused : std_logic; signal clkout2_unused : std_logic; signal clkout2b_unused : std_logic; signal clkout3_unused : std_logic; signal clkout3b_unused : std_logic; signal clkout4_unused : std_logic; signal clkout5_unused : std_logic; signal clkout6_unused : std_logic; -- Dynamic programming unused signals signal do_unused : std_logic_vector(15 downto 0); signal drdy_unused : std_logic; -- Dynamic phase shift unused signals signal psdone_unused : std_logic; signal locked_int : std_logic; -- Unused status signals signal clkfbstopped_unused : std_logic; signal clkinstopped_unused : std_logic;
begin

-- Input buffering --------------------------------------clk_in1_clk_wiz_0 <= clk_in1;

-- Clocking PRIMITIVE -------------------------------------- -- Instantiation of the MMCM PRIMITIVE -- * Unused inputs are tied off -- * Unused outputs are labeled unused mmcm_adv_inst : MMCME2_ADV generic map (BANDWIDTH => "OPTIMIZED", CLKOUT4_CASCADE => FALSE, COMPENSATION => "ZHOLD", STARTUP_WAIT => FALSE, DIVCLK_DIVIDE => 1, CLKFBOUT_MULT_F => 10.125, CLKFBOUT_PHASE => 0.000, CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_DIVIDE_F => 25.3125, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT0_USE_FINE_PS => FALSE, CLKIN1_PERIOD => 10.0, REF_JITTER1 => 0.010) port map -- Output clocks ( CLKFBOUT => clkfbout_clk_wiz_0, CLKFBOUTB => clkfboutb_unused, CLKOUT0 => clk_out1_clk_wiz_0, CLKOUT0B => clkout0b_unused, CLKOUT1 => clkout1_unused, CLKOUT1B => clkout1b_unused, CLKOUT2 => clkout2_unused, CLKOUT2B => clkout2b_unused, CLKOUT3 => clkout3_unused, CLKOUT3B => clkout3b_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, CLKOUT6 => clkout6_unused, -- Input clock control CLKFBIN => clkfbout_buf_clk_wiz_0, CLKIN1 => clk_in1_clk_wiz_0, CLKIN2 => '0', -- Tied to always select the primary input clock CLKINSEL => '1', -- Ports for dynamic reconfiguration DADDR => (others => '0'), DCLK => '0', DEN => '0', DI => (others => '0'), DO => do_unused, DRDY => drdy_unused, DWE => '0', -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => psdone_unused, -- Other control and status signals LOCKED => locked_int, CLKINSTOPPED => clkinstopped_unused, CLKFBSTOPPED => clkfbstopped_unused, PWRDWN => '0', RST => '0');

-- Output buffering -------------------------------------
clkf_buf : BUFG port map (O => clkfbout_buf_clk_wiz_0, I => clkfbout_clk_wiz_0);

clkout1_buf : BUFG port map (O => clk_out1, I => clk_out1_clk_wiz_0);

end xilinx;

Constraints

set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {clk_in}];create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_in}];
set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_hsync }]; #IO_L4P_T0_15 Sch=vga_hsset_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_vsync }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[2] }]set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[3] }]set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[3] }]set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[3] }]
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ADC_SDATA1 }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ADC_SDATA2 }]; #IO_L21P_T3_DQS_15 Sch=ja[3]set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ADC_SCLK }]; #IO_L18N_T2_A23_15 Sch=ja[4]set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ADC_CS }]; #IO_L20N_T3_A19_15 Sch=ja[1]
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btn0 }]; #IO_L9P_T1_DQS_14 Sch=btnc

Synthesis and Implementation