Ph.D. Student @ University of California, Davis
Analog & Mixed-signal IC designer
Cheng Li received the B.Eng degree in Microelectronic from Sun Yat-Sen University (SYSU), Guangzhou, China, in 2014, and M.Sc. degree in Electrical and Computer Engineering, University of Macau, Macau, China, in 2018. He is currently pursuing his Ph.D. degree in Electrical and Computer Engineering, University of California, Davis (UCDavis), CA, USA.
He was with the State key Laboratory of Analog and Mixed-signal VLSI (AMSV), University of Macau, during Aug. 2014-Jun. 2018, where his research interest included analog and mixed-signal IC design, with a focus on the power management in high-speed SAR ADC design, such as Low-dropout regulator (LDO) and reference buffer.
His current research interest is RF/mmWave integrated circuit design.
Email: email@example.com / firstname.lastname@example.org
Address: Engineering Office BLDG., TB207, University of California, Davis, U.S.A.
- C. Li, C. H. Chan, Y. Zhu, R. P. Martins, "Analysis and Modeling for Reference Error in High Speed SAR ADCs with Capacitive DAC," in IEEE Transactions on Circuits and Systems I (TCAS-I), 2019. (DOI: 10.1109/TCSI.2018.2861835 )
- G. Wang, C. Li, Y. Zhu, Y. Lu, J. Zhong, C. H. Chan, R. P. Martins, “Missing-code-occurrence Probability Calibration Technique with Supply and Reference Circuit Analysis to Achieve High Linearity DAC,” in IEEE Transactions on Circuits and Systems I (TCAS-I), 2018. (DOI: 10.1109/TCSI.2018.2858848 )
- Y. Zhu, C. H. Chan, Z. Zheng, C. Li, J. Zhong, S. P. U, R. P. Martins, "A 0.19mm2 10b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65nm CMOS," in IEEE Transactions on Circuits and Systems I (TCAS-I), 2018. (DOI: 10.1109/TCSI.2018.2858848)
- C. H. Chan, Y. Zhu, C. Li, W. H. Zhang, I. M. Ho, L. Wei, S. P. U, R. P. Martins, "60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration," in IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 10, pp. 2576-2588, Oct. 2017.
- Y. Lu, C. Li, Y. Zhu, M. Huang, S. P. U and R. P. Martins, "A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS," Electronics Letters (EL), vol. 52, no. 16, pp. 1368-1370, 2016.
- Circuit design: Cadence, Hspice, Altium designer
- Programming: C, Matlab, Verilog HDL
- Others: Visio, Photoshop