Bernard Tran

[2020-01-23] Week 1 Report

• Created Website for dsd
• Created GitHub repository for dsd
• Installed Vivado and downloaded board files

[2020-01-30] Week 2 Report

• Covered Chapter 3 and 4 in class lectures

[2020-02-06] Week 3 Report

• Covered Chapter 5 and 6 in class
• Completed steps until hardware manager, waiting for board to program device

[2020-02-13] Week 4 Report

• Covered Chapter 7 and 8 in class
• Completed Lab 1 Project 1 and 2 in class
  • Followed instructions on GitHub and the device was able to switch hexadecimal numbers using different places on the 7 segment decoder
    • Switch 6 and 7 changed the which place on the 7 segment decoder the hex numbers appeared
    • Switches 0, 1, 2, and 3 changed which hex number was displayed according to the binary input on the switches
  • Hexcount allowed the device to count from 0 to F on the least significant bit on the left module the right module displayed all digits

[2020-02-20] Week 5 Report

• Covered Chapter 9 in class
  • Structural Modeling, Adding Components into VHDL
• Started Lab 2

[2020-02-27] Week 6 Report

• Covered Chapter 10 and 11 in class
  • Registers, Signals and Variables
• Completed Lab 2 in class
  • The 4 digit counter does not start if the device is booted from JTAG, the FPGA only boots from QSPI (blue MODE jumper)

[2020-03-05] Week 7 Report

• Started Lab 3: VGA

[2020-03-12] Week 8 Report

• Covered Chapter 12 in class: Loops
  • For loops and while loops

[2020-03-19] Spring Break

[2020-03-26] Week 9 Report

• Continuing Lab 3 to work with personal monitor
  • Changed the frequency of vga_sync
• Committed changes from lab 3 to GitHub

[2020-04-02] Week 10 Report

• Beginning to formulate ideas for semester project
• Correctly formatted GitHub for only DSD projects
• Starting On lab 4

[2020-04-09] Week 11 Report

• Updating Project Proposal
• Currently working on labs
• Researched into Ethernet communication on Nexys A7 and Nexys 4 DDR
  • https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start
  • https://www.fpga4fun.com/10BASE-T0.html?_ga=2.198526447.1188673323.1586277362-1711081422.1579720180
  • https://forum.digilentinc.com/topic/1382-how-to-implement-ethernet-project-on-nexys-4-ddr/
    • Possible to use a separate Ethernet Pmod to expand the ports
    • There is a separate IC (integrated circuit) between the on board Ethernet port and the actual FPGA
    • Its easier to use a Microblaze server to communicate over the on-board Ethernet

[2020-04-16] Week 12 Report

• Continuing research on project
  • https://www.reddit.com/r/FPGA/comments/c08djp/questions_on_constraints_clocking_in_nexys_a7/
  • https://store.digilentinc.com/pmod-nic100-network-interface-controller/

[2020-04-23] Week 13 Report

• Completed leading 0 suppression for lab 4
• Also, the numbers also display from right to left more like a normal calculator

anode <= "0111" WHEN dig = "00" AND data /= X"0000" ELSE -- digit 0

         "1011" WHEN dig = "01" AND data(15 downto 4) /= X"000" ELSE -- digit 1

         "1101" WHEN dig = "10" AND data(15 downto 8) /= X"00" ELSE -- digit 2

         "1110" WHEN dig = "11" AND data(15 downto 12) /= X"0" ELSE -- digit 3

         "1111";

• Starting work on the project as well
  • Created constrain file for the project

[2020-04-30] Week 14 Report

• Update project documentation for Ethernet RMII standard on board
• Beginning documentation on main design file
• Updated project documentation page

[2020-05-05] Week 15 Report

• Updating project documentation
• Working on lab 5

[2020-05-14] Week 15 Report

• Completed Lab 5 and Lab 6
• Finalized Project