最新の研究成果

1. R. Sumikawa, A. Kosuge, Y. C. Hsu, K. Shiba, M. Hamada, T. Kuroda "A183.4-nJ/inference 152.8-μW 35-Voice Commands Recognition Wired-Logic Processor Using Algorithm-Circuit Co-Optimization Technique," in IEEE Solid-State Circuits Letters, vol. 7, pp. 22-25, 2024.

2. D. Li, Z. Zhan, R. Sumikawa, M. Hamada, A. Kosuge, T. Kuroda "A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA," in IEICE Trans. Electronics (Accept, in Press).  

3. A. Kosuge, Y. C. Hsu, R. Sumikawa,T. Ishikawa, M. Hamada, and T. Kuroda, "A 10.7-μJ/frame 88% Accuracy CIFAR-10 Single-chip Neuromorphic FPGA Processor Featuring Various Nonlinear Functions of Dendrites in Human Cerebrum," in IEEE Micro, vol. 43, no. 6, pp. 19-27, Nov.-Dec. 2023. 

4. A. Kosuge, L. Yu, M.Hamada, K. Matsuo, T. Kuroda, "A Deep Metric Learning-Based Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion " in IEEE Open Journal of the Industrial Electronics Society, vol. 4, pp. 205-213, June 2023.

5. K. Shiba, M. Okada, A. Kosuge, M. Hamada and T. Kuroda, "Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication with Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers,  vol. 70, no. 9, pp. 3440-3450, Sept. 2023.

6. K. Shiba, M. Okada, A. Kosuge, M. Hamada and T. Kuroda, "A 12.8-Gb/s 0.5-pJ/b Encoding-less Inductive Coupling Interface Achieving 111-GB/s/W 3D-Stacked SRAM in 7-nm FinFET," in IEEE Solid-State Circuits Letters, vol. 6, pp. 65-68, March 2023.

7. R. Sumikawa, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "1.2-nJ/classification 2.4-mm 2 asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18-µm CMOS," in Japanese Journal of Applied Physics, vol. 62, pp. SC1019-1 SC1019-8, Jan. 2023.

8. K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda, "A 7-nm FinFET 1.2-TB/s/mm^2 3D-Stacked SRAM Module with 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-encoded Synchronous Transceiver," in IEEE Journal of Solid-State Circuits, vol. 58, no. 7, pp. 2075-2086, July 2023 vol. 58, no. 7, pp. 2075-2086, July 2023.

9. S. Shibata, R. Miura, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A 5-GHz 0.15-mm^2 Collision-Avoiding RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna in 0.18-μm CMOS," in IEEE Solid-State Circuits Letters (SSC-L), vol. 5, no. 11, pp. 268-271, Nov. 2022.

10. A. Kosuge and T. Kuroda, "[Invited] Proximity Wireless Communication Technologies: An Overview and Design Guidelines," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 11, pp. 4317-4330, Nov. 2022 (Selected as highlight paper on November issue). 

11. K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface," IEICE Transactions on Electronics, vol. E106-C, no. 7, pp. 391-394, July 2023. 

12. A. Kosuge, M. Hamada, S. Suehiro, and T. Kuroda, "mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multi-Class Object Recognition System for ADAS Applications," IEEE Transactions on Instrumentation and Measurements, vol. 71, pp. 1-10, May 2022.

13. A. Kosuge, M. Hamada, and T. Kuroda, "A 6.5 Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System," IEICE  Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 105-A, no. 3, pp. 478-486, Mar. 2022.

14. M. Reiji, S. Shibata, M. Usui, A. Kosuge, M. Hamada, T. Kuroda, "A bonding-less 5-GHz RFID module using inductive coupling between IC and antenna," in Japanese Journal of Applied Physics (JJAP), vol. 61, no. SC1058, pp. 1-9, Feb. 2022.

15. A. Kosuge, M. Hamada, and T. Kuroda, "A 6-Gb/s Inductively-Powered Non-Contact Connector with Rotatable Transmission Line Coupler and Interface Bridge IC," IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 535-545, Feb. 2022.

16. A. Kosuge, Y. Hsu, M. Hamada, and T. Kuroda, "A 0.61-μJ/frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network," IEEE Open Journal of Circuits and Systems, vol. 3, pp. 4-14, Jan. 2022.

17. A. Kosuge, M. Hamada, and T. Kuroda, "A 16nJ/Classification FPGA-based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 11, no. 4, pp. 751-761, Dec. 2021. 

18. A. Kosuge, K. Yamamoto, Y. Akamine, and T. Oshima, "An SoC-FPGA based Iterative Closest Point Accelerator Enabling Faster Picking Robots," IEEE Trans. on Industrial Electronics, vol. 68, no. 4, pp. 3567-3576, April 2021.

19. V. Crescitelli, A. Kosuge, and T. Oshima, "POISON: Human Pose Estimation in Insufficient Lightning Conditions Using Sensor Fusion," IEEE Trans. on Instruments and Measurements, vol. 70, Article Number 2504408, Jan. 2021.

20.  J. Kadomoto, S. Hasegawa, Y. Kiuchi, A. Kosuge, and T. Kuroda, "Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO," IEICE Trans. on Electronics, vol. E99-C, no. 6, pp. 659-662, June 2016. 

21. A. Kosuge, J. Kadomoto, and T. Kuroda, "A 6 Gb/s 6 pJ/b 5mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver," IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 6, pp. 1446-1456, June 2016. 

22. A. Kosuge, J. Hashiba, T. Kawajiri, S. Hasegawa, T. Shidei, H. Ishikuro, T. Kuroda, and K. Takeuchi, "An Inductively-Powered Wireless Solid-State Drive System with Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories," IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 4, pp. 1041-1050, Apr. 2016. 

23. A. Kosuge, A. Okada, M. Taguchi, H. Ishikuro, and T. Kuroda, "A 280Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver," IEEE Trans. on Circuits and Systems-I: Regular Papers (TCAS-I), vol. 63, no. 2, pp. 265-275, Feb. 2016. 

24. L. Hsu, J. Kadomoto, S. Hasegawa, A. Kosuge, Y. Take, and T. Kuroda, "A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E98-A, no. 12, pp. 2584-2591, Dec. 2015. 

25. A. Kosuge, S. Ishizuka, M. Taguchi, H. Ishikuro, and T. Kuroda, "Analysis and Design of an 8.5-Gb/s/link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers," IEEE Trans. on Circuits and Systems-I: Regular Papers (TCAS-I), vol. 62, no. 8, pp. 2122-2131, Aug. 2015. 

26. A. Kosuge, W. Mizuhara, T. Shidei, T. Takeya, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda,  "A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler," IEEE Journal of Solid-State Circuits (JSSC), vol. 49, no. 1, pp. 223-231, Jan. 2014. 

27. A. Kosuge, T. Takeya, M. Shioya, M. Taguchi, and T. Kuroda, "A 3 Gbps Non-Contact Inter-Module Link with Twofold Transmission Line Couplers and Low Frequency Compensation Equalizer," Japanese Journal of Applied Physics (JJAP), vol. 52, no. 4, Apr. 2013. 

1. D. Li, T. Zhao, K. Kobayashi, A. Kosuge, M. Hamada, T. Kuroda, "Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions," in IEEE International Symposium on Circuits and Systems (ISCAS), May, 2024 (To be presented).

2. E. Kobayashi, A. Kosuge, M. Hamada, T. Kuroda, "An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique," in 49th Annual Conference of the IEEE Industrial Electronics Society (IECON), Oct. 2023. 

3. A. Kosuge, R. Sumikawa, Y. -C. Hsu, K. Shiba, M. Hamada, T. Kuroda, "A 183.4nJ/inference 152.8uW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application," in IEEE Symposium on VLSI Circuits, June 2023.

4. X. Wang, A. Kosuge, Y. Hayashi, K. Shiba, M. Hamada, T. Kuroda, "Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application," International New Circuits and Systems Conference (NEWCAS), June 2023.

5. N. Shimamto, A. Mizushima, D. Bourrier, E. Ota, A. Higo, H. Granier, A. Kosuge, M. Ikeda, T. Kuroda, and Yoshio Mita, "Micron-to-Submicron Cu electroplating in view of Agile-X LSI Chips Fabrication using Open Facility", 3rd European Nanotechnology Research Infrastracture Symposium (ENRIS 2023), May, 2023.

6. D. Li, Y. -C. Hsu, R. Sumikawa, A. Kosuge, M. Hamada, T. Kuroda, "A 0.13mJ/prediction CIFAR-100 Raster-Scan-Based Wired-logic Processor Using Non-linear Neural Network" in IEEE International Circuits and Systems (ISCAS), May 2023.

7. Y. Hsu, A. Kosuge, R. Sumikawa, K. Shiba, M. Hamada, T. Kuroda, "A Fully Synthesized 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network," IEEE 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2023.

8. R. Sumikawa, K. Shiba, A. Kosuge, M. Hamada, T. Kuroda, "A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-linear Function Blocks in 0.18µm CMOS," IEEE 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2023.

9. K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda, “A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-Stacked SRAM in 7-nm FinFET,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2022. 

10. X. Wang, A. Kosuge, Y. Hayashi, M. Hamada, and T. Kuroda, "A 7 Gb/S Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shield Vias," in 29th IEEE International Conference on Electronics Circuits and Systems(ICECS 2022), Oct. 2022.

11. S. Shibata, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic," in 29th IEEE International Conference on Electronics Circuits and Systems(ICECS 2022), Oct. 2022.

12. R. Sumikawa, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A 1.2nJ/Classification 2.4mm2 Wired-Logic Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18um CMOS," JSAP International Conference on Solid State Devices and Materials (SSDM'22), Extended Abstracts, pp. 750-751, Sep. 2022.

13. S. Shibata, R. Miura, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A 5-GHz 0.15-mm^2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna (Invited)," IEEE 48th European Solid-State Circuits Conference (ESSCIRC 2022), Sep. 2022.

14. Y. C. Hsu, A. Kosuge, R. Sumikawa, K. Shiba, M. Hamada and T. Kuroda, "A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA Using Non-Linear Neural Network," in Proc. IEEE Hot Chips Symposium (HC'22), Aug. 2022. 

15. K. Shiba, M. Okada, A. Kosuge, M. Hamada and T. Kuroda, "A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers," in Proc. IEEE Hot Chips Symposium (HC'22), Aug. 2022. 

16. L. Yu, A. Kosuge, M. Hamada, and T. Kuroda, "An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique" in IEEE Sensors Application Symposiun (SAS'22), Aug. 2022.

17. K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda, "Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format," in IEEE International New Circuits and Systems Conference (NEWCAS), June 2022.

18. R. Miura, S. Shibata, M. Usui, A. Kosuge, M. Hamada, and T. Kuroda, "A 5.2GHz RFID Chip Contactlessly Mountable on FPC at Any 90-Degree Rotation and Face Orientation," in IEEE 27th Asia and South Pacific Design Automation Conference (ASP-DAC'22), Dig. Tech. Papers,  pp. 5-6, Jan. 2022.

19. T. Omori, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A Physical Verification Methodology for 3D-ICs Using Inductive Coupling," IEEE Electrical Design of Advanced Packaging and Systems(EDAPS), pp. 72-74, Dec. 2021. 

20. S. Shibata, R. Miura, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna," IEEE Asian Solid-State Circuits Conference (A-SSCC'12), Dig. Tech Papers, pp. 1-3, Nov. 2021.

21. R. Miura, S. Shibata, M. Usui, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda, "A Bonding-less 5-GHz RFID Module Using a 300um x 500um IC Chip," JSAP International Conference on Solid State Devices and Materials (SSDM'21), Extended Abstracts, pp. 686-687, Sep. 2021. 

22.  A. Kosuge and T. Oshima, "A 1200x1200 8-Edges/Vertex FPGA-based Motion- Planning Accelerator for Dual-Arm-Robot Manipulation Systems," IEEE Symposium on VLSI Circuits (VLSI’20), Dig. Tech. Papers, pp. CA2.5.1-2.5.2, June 2020. 

23.  V. Crescitelli, A. Kosuge, and T. Oshima, "An RGB/Infra-Red Camera Fusion Approach for Multi-Person Pose Estimation," Proc. IEEE Sensors Applications Symposium (IEEE SAS 2020), pp. 1-6, March 2020. 

24. A. Kosuge and T. Oshima, "An Object-Pose Estimation Acceleration Technique for Picking Robot Applications by Using Graph-Reusing k-NN Search," Proc. IEEE Graph-Computing (GC 2019), pp. 68-74, Sep, 2019. 

25. A. Kosuge, K. Yamamoto, Y. Akamine, T. Yamawaki, and T. Oshima, "A 4.8x Faster FPGA-Based Iterative Closest Point Accelerator for Object Pose Estimation of Picking Robot Applications," IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’19), p. 331, April 2019. 

26. M. Haraguchi, A. Kosuge, T. Igarashi, S. Masaki, M. Sueda, M. Hamada, and T. Kuroda, "A 6Gb/s Rotatable Non-Contact Connector with High-Speed/I2C/CAN/SPI Interface Bridge IC," IEEE Symposium on VLSI Circuits (VLSI’17), Dig. Tech. Papers, pp. C150-C151, June 2017. 

27. H. Itakura, Y. Akeboshi, H. Yamada, H. Yoshiko, S. Ichikawa, A. Kosuge, M. Haraguchi, and T. Kuroda, "Basic Study of Non-Contact Connector for High-Speed Space Cable Transmission," International SpaceWire Conference (ISC’16), Short Paper, Oct. 2016. 

28. S. Hasegawa, J. Kadomoto, A. Kosuge, and T. Kuroda, "A 1 Tb/s/mm2 Inductive-Coupling Side-by-Side Chip Link," Proc. IEEE European Solid-State Circuits Conference (ESSCIRC’16), pp. 469-472, Sep. 2016. 

29. L. Hsu, J. Kadomoto, S. Hasegawa, A. Kosuge, Y. Take, and T. Kuroda, "Analytical ThruChip Inductive Coupling Channel Design Optimization," 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 731-736, Jan. 2016. 

30. A. Kosuge, J. Hashiba, T. Kawajiri, S. Hasegawa, T. Shidei, H. Ishikuro, T. Kuroda, and K. Takeuchi, "Inductively-Powered Wireless Solid-State Drive (SSD) System with Merged Error Correction of High-Speed Non-Contact Data Links and NAND Flash Memory," IEEE Symposium on VLSI Circuits (VLSI’15), Dig. Tech. Papers, pp. C128-C129, June 2015. 

31. A. Kosuge, S. Ishizuka, M. Abe, S. Ichikawa and T. Kuroda, "A 6.5Gb/s Shared Bus using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System by 60%," IEEE International Solid-State Circuits Conference (ISSCC’15), Dig. Tech. Papers, pp. 434-435, Feb. 2015. 

32. A. Kosuge, S. Ishizuka, J. Kadomoto, and T. Kuroda, "A 6Gb/s 6pJ/b 5mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and EMC-Qualified Pulse Transceiver," IEEE International Solid-State Circuits Conference (ISSCC’15), Dig. Tech. Papers, pp. 176-177, Feb. 2015.

33. L. Hsu, Y. Take, A. Kosuge, S. Hasegawa, J. Kadomoto, and T. Kuroda,  "Design and Analysis for ThruChip Design for Manufacturing (DFM)," 20th Asia and South Pacific Design Automation Conference , Proceedings, pp. 46-47, Jan. 2015. 

34. A. Okada, A. Raziz Junaidi, Y. Take, A. Kosuge, and T. Kuroda, "Circuit and Package Design for 44GB/s Inductive-Coupling DRAM/SoC Interface," 20th Asia and South Pacific Design Automation Conference, Proceedings, pp. 44-45, Jan. 2015. 

35. A. Kosuge, S. Ishizuka, L. Liu, A. Okada, M. Taguchi, H. Ishikuro, and T. Kuroda,  "An Electromagnetic Clip Connector for In-Vehicle LAN to Reduce Wire Harness Weight by 30%," IEEE International Solid-State Circuits Conference (ISSCC’14), Dig. Tech. Papers, pp. 496-497, Feb. 2014. 

36. W. Mizuhara, T. Shidei, A. Kosuge, T. Takeya, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda, "A 0.15mm-Thick Non-Contact Connector for MIPI Using Vertical Directional Coupler," IEEE International Solid-State Circuits Conference (ISSCC’13), Dig. Tech. Papers, pp. 200-201, Feb. 2013. 

37. A. Kosuge, W. Mizuhara, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda,
    "A 12.5Gb/s/Link Non-Contact Multi-Drop Bus System with Impedance-Matched Transmission Line Couplers and Dicode Partial-Response Channel Transceivers," 18th Asia and South Pacific Design Automation Conference (ASP-DAC’13), pp. 91-92, Jan. 2013. 

38. A. Kosuge, T. Takeya, M. Shioya, M. Taguchi, and T. Kuroda, "A 3Gb/s Non-Contact Inter-Module Link with Duplex Transmission-Line-Couplers and Low-Frequency Compensation Equalizer," JSAP International Conference on Solid State Devices and Materials (SSDM’12), Extended Abstracts, pp. 1152-1153, Sep. 2012. 

39. A. Kosuge, W. Mizuhara, N. Miura, M. Taguchi, H. Ishikuro, and T. Kuroda,
    "A 12.5Gb/s/Link Non-Contact Multi Drop Bus System with Impedance-Matched Transmission Line Couplers and Dicode Partial-Response Channel Transceivers,"
    in Proc. IEEE Custom Integrated Circuits Conf. (CICC’12), pp. 7.9.1-7.9.4, Sep. 2012. 

40. W. Yun, S. Nakano, W. Mizuhara, A. Kosuge, N. Miura, H. Ishikuro, and T. Kuroda, "A 7Gb/s/Link Non-Contact Memory Module for Multi-Drop Bus System Using Energy-Equipartitioned Coupled Transmission Line," IEEE International Solid-State Circuits Conference (ISSCC’12), Dig. Tech. Papers, pp. 52-53, Feb. 2012. 

1. 柴康太, 小菅敦丈, 濱田基嗣、黒田忠広,
   "近接場無線接続技術を用いた三次元積層SRAM,"
   エレクトロニクス実装学会誌, vol. 25, no. 6, pp. 549-555, Sep. 2022. 

2. 岡田晃, 小菅敦丈, 黒田忠広,
   "近接場結合を用いたLSIとモジュールの三次元集積,"
   電子情報通信学会論文誌, vol. J97-C, no. 11, pp. 378-385, Nov. 2014. 

1. Tadahiro Kuroda and Atsutake Kosuge,
   "VLSI Design and Test for Systems Dependability (Chapter21: Wireless Interconnect in Electronic Systems),"
   ISBN 978-4-431-56592-5, Springer, 2019.

2. Tadahiro Kuroda and Atsutake Kosuge,
   "VLSI Design and Test for Systems Dependability (Chapter8: Connectivity in Electronic Packaging) ,"
   ISBN 978-4-431-56592-5, Springer, 2019.

1. 日経エレクトロニクス　ジャパン・ワイヤレス・テクノロジー・アワード 最優秀賞 (日経エレクトロニクス、2013年5月)

2. 藤原賞 (慶應義塾大学、2014年3月)

3. 2015 ASP-DAC Special Feature Award (ASP-DAC、2015年1月)

4. University Research Competition Finalist (Broadcom Foundation、2015年6月)

5. 日経エレクトロニクス　アナログ・イノベーション・アワード
   読者賞 (日経エレクトロニクス、2017年1月)

6. 優秀研究活動賞 (慶應義塾大学、2017年3月)

7. 学術奨励賞 (電子情報通信学会、2020年3月)

8. MIT Technology Review Japan Innovators Under 35 (2021年12月)

1. [研究代表者]  マツダ財団「マツダ研究助成」 (2021年11月~)

2. [研究代表者]  JST「さきがけ」 (2021年10月~)

3. [研究代表者]  科研費「研究活動スタート支援」 (2021年10月~)  

4. [研究代表者]  NEDO「官民による若手研究者発掘支援事業」 (2021年7月~) 

5. [研究代表者] 日本学術振興会特別研究員　DC1 科研費 (2014年4月~2017年3月)

1. 小菅敦丈, "[招待講演] 布線論理型アーキテクチャによる、デジタルニューロモルフィックプロセッサ," 電子情報通信学会総合大会, Mar. 2024.

2. A. Kosuge, "Agile Edge AI Design and Fabrication," Japanese-French-Scottish Open Workshop on Agile AI LSI design and fabrication, Oct. 2023.

3. A. Kosuge, "Digital neuromorphic computing systems featuring dendrite-spines in human cerebrum [Invited]," The 18th D2T Symposium, Sep. 2023

4. 小菅敦丈, "[招待講演] 半導体回路設計製造の民主化拠点 :Agile-X" 電子情報通信学会総合大会, Mar. 2023.

5. A. Kosuge, “Energy-efficient Neuromorphic Processor for In-Sensor Computing ,”  Workshop on Trusted Cyber Physical Cognitive System, Japan India Joint Research Hub, Indian Institute of Technology Bombay, Feb. 2023. 

6. A. Kosuge, “Computational Sensing Technologies for Cyber-Physical Systems,” Princeton University, EE-Department Seminar, Sep. 2022. 

7. 小菅敦丈, “FPGAによる超低電力布線論理型AIプロセッサ,” 情報処理学会 DAシンポジウム, Sep. 2022. 

8. A. Kosuge, "Computational Sensing Technologies for Cyber-Physical Infrastructure (invited)," IEEE Symposium on VLSI Circuits, Friday Forum, June 2022. 

9. 柴康太, 小菅敦丈, 濱田基嗣, 黒田忠広,
   "三次元積層SRAMと近接場無線接続技術,"
   集積回路研究会(ICD), April, 2022.

10. 小菅敦丈, “オンデバイス教師なし学習型ＡＩ外観検査ソリューションの研究開発” 経産省・NEDO 若手研究者の研究シーズ紹介イベント, Feb. 2022. 

11. 小菅敦丈,
    "社会課題解決に向けたAIチップの研究,"
    集積システム材料産学連携コンソーシアム, Jan. 2022.

12. 小菅敦丈,
    "超低電力AIプロセッサ,"
    MIT Technology Review, Innovators Under 35 Japan Summit 2021, Dec 2021.

13. 小菅敦丈，門本淳一郎，黒田忠広
    "伝送線路型結合器を用いた非接触メモリインタフェース，"
    集積回路研究会(ICD), April 2015.

14. 小菅敦丈,
    "ワイヤレスSSDに向けた高速通信技術,"
    CEATEC 2013, Oct. 2013. 

15. 小菅敦丈, 水原渉, 四手井綱章, 竹谷勉, 三浦典之, 田口眞男, 石黒仁揮, 黒田忠広,
    "方向性結合器を用いた携帯機器用途向け0.15mm厚非接触コネクタ,"
    シリコン材料・デバイス研究会(SDM)/集積回路研究会(ICD), Aug. 2013. 

16. 小菅敦丈,
    "ワイヤレスSSDに向けた高速通信技術,"
    NE ジャパン・ワイヤレス・テクノロジー・アワード受賞記念講演, May 2013. 

[1] Three-dimensional position and posture recognition device and method US Patent App. 17/295,148

[2] 特願2021-138412 情報処理装置、及びプログラム 

[3] 特願2021-076487 機械学習回路及び情報処理装置 

[4] 特願2019-37788 学習装置および学習方法 

[5] 特願2018-239421 ３次元位置・姿勢認識装置及び方法 

[6] 特願2018-117762 ニューラルネットワーク回路 

[1] "小菅敦丈：AIによる電力危機を救う半導体研究者" MIT Technology Review Japan, vol. 6, 2022年3月.

[2] "Princeton-University of Tokyo Strategic Partnership Celebrates

In-Person Collaboration," PRINCETON INTERNATIONAL, 2022年11月8日. 

[3] "半導体強く、僕らの世代で 「脳」のように超省電力に," 日本経済新聞, 2022年12月19日. 

[4] “東大とJST、音声コマンド認識AIの消費電力を3桁削減可能な布線論理型AIプロセッサを開発,” 日本経済新聞, 2023年6月9日. 

[5] “音声コマンド認識ＡＩの電力を３桁削減するＡＩプロセッサー,” NEXT MOBILITY, 2023年6月9日. 

[6] “東大など、従来より3桁以上消費電力が少ないAIプロセッサを開発,”

日経XTECH, 2023年6月12日.

[7] “東大、音声コマンド認識AI向け省電力プロセッサを開発。乾電池1本で2.2年連続動作,” PC Watch, 2023年6月12日. 

[8]  "消費電力2552分の1のAIプロセッサー," JSTnews９月号 NEWS&TOPICS, 2023年9月.