-Built an initial draft of a website for the course and looked over the syllabus

-Briefly introduced VHDL and how to download and install the required software

-Reviewed Chapter 3 in the textbook

-Learned about library and entity declaration coding as well as signal and variable assignment architecture

-Reviewed Chapter 4 and learned about conditional signal assignments with logic gates and bit inputs/outputs

-Viewed signal waves in a VHDL program

-Reviewed all the way up to chapter 6 in the textbook

-Went over sequential statements and behavior processes

-Began to cover Lab 1 Part A; learned how to write arithmetic and logical statements with shifting and rotating bits

-Learned how to connect and turn on the FPGA board and initialize a project

• Worked on and completed Lab 1 (see "Labs" tab).

• Began to cover Chapter 9; Talked more about hexcount and modularity (components) as well as structural modeling overall
• Spoke about parity check implementation within generic mapping
• Went into Vivado/GitHub and received an explanation on how exactly to conduct Lab 2, as well as a mini demonstration using the FPGA board

• Continued to work on and finish Lab 2 (see "Labs" tab)
• Reviewed Chapter 11 and learned about scheduling events in terms of variables and signals
• Briefly covered the standard data types and user-defined types

• No class on Tuesday or Thursday due to Professor Lu traveling

• No class Tuesday due to COVID-19
• On Thursday, we reviewed and discussed Chapter 12 as well as an updated plan on how to proceed for the rest of the semester online

• No class due to spring break

• Went over Chapter 12 and talked about looping constraints
• Discussed website updates and a plan going forward in regards to COVID outbreak and online class

• Went over website fixes; published visible GitHub link and made lab videos available for public viewing
• COVID-19 outbreak has made it difficult to conduct lab work due to having no access to a board or Vivado; Professor Lu recommends watching videos on YouTube to still be able to learn about VHDL

• Continued to review websites and applicable fixes; Updated my site to reflect requested changes

• Professor Lu showed off GHDL and where to find it on GitHub
• Downloaded GHDL v0.37 for MacOSX off GitHub and followed instructions for installations
• Currently in process of testing and running the software

• Finalized project for the class (See "Project" tab)

• Began working over Zoom sessions with Anthony on the project
• Able to successfully rebuild and recreate a functional Tetris game (video added to "Projects" tab)
• Professor Lu suggested conducting work with GTKWave; I will look into this during the upcoming weekend

• Got GTKWave and GHDL to run on my Mac (see "Labs" Tab)
• Final class period for the semester; Finalizing website by May 15th deadline
• Added all project code to GitHub
• Finishing GTKWave analysis for labs