Weekly Reports:

Reviewed chapters 4-9 of the Free Range VHDL Textbook. - Will be taking extensive notes and doing practice problems in week 3 -. I am not partnered with classmate Eugene K. for an in class FPGA project. Updated plugins for Xilinx

Reviewed chapters 10-12 of Free Range VHDL. Partner obtained Nexys A7-100T and a Keypad Pmod.

A wise man once told me that a great student of any kind not only climbs on the backs of the students before him, but also becomes a trailblazer themselves to help future students as well. In an attempt to both heed to the advice and learn myself, I decided to take condensed notes based on the in class textbook for VHDL. This will hopefully condense about 170 pages to approximately 30. However, due to becoming sick, I was unable to continue and had only managed to go to around page 30. This will outline all the important and vital information that should be instilled in any VHDL programmer, so far I was able to collectively condense 30 pages to 5.

Redesigned website.

New partner, Michael Dasaro, is now in our group.

GitHub Repo to be updated this week upon receiving and testing FPGA and VHDL codes.

Lab 4 set up in Vivado in preparation to test once hardware is received.

Will pickup FPGA from Doctor Lu.

Notes for VHDL Textbook are to be put on pause during exam week.

Brainstormed idea for final project with my group (10).

Ideas:

Color recognition on the FPGA. We want to try to go through an image file and filter out the pixels that are in a certain color range, comparable to OpenCV libraries. Our simplest goal would be to read a PNG from the SD card and set every pixel that isn't in the desired range to (0,0,0), leaving only the color range that we want.

Another idea thrown recently was a tower defense game. This one would be much more fun and interactive, which should lead to faster development.

Looked over the new hex counting lab code.

Collaborated with team in brainstorming more ideas for final project.

Considered different methods of approach to final project idea.

Will resume working on textbook notes this week.

Team set up team GitHub repository for resources, ideas, and code to build on final project.

https://github.com/EKozlakov/CPE487A-DSD

Resources found:

https://www.fpga4student.com/2016/11/image-processing-on-fpga-verilog.html

https://www.fpga4student.com/

Found camera for FPGA: Photo below with link.

https://www.ebay.com/itm/VGA-OV7670-CMOS-Camera-Module-Lens-CMOS-640X480-SCCB-W-I2C-Interface-Arduino-/201414930886

Due to an extensive number of interviews and outside work, I was unable to work at maximum capacity this week, however I will note what I had completed nonetheless.

Worked on Lab 4.

Successfully completed all base modifications. Worked with team mate Eugene but failed to implement negative/signed numbers into Lab 4 "HexCalc."

Massive GitHub load drop in the upcoming days. Due to the fact that I had transferred over to a another computer, I have to set up SSH again, as well as redo basic environmental steps. Not a huge deal, but due to the time constraint it must be prioritized low for myself.

Will also work to set up meeting with Doctor Lu in the next 2-3 lectures, there is some catching up to do and some other educational affairs outside of the class to attend to.

Began work on final project.

Successfully implemented VHDL file using code from FPGA4student. - https://www.fpga4student.com/2018/08/how-to-read-image-in-vhdl.html

Next step would be to implement the "proof of concept" function by displaying the bits that the VHDL code reads. Group will work on potentially implementing "leddec" project file to display these bits.

Good progress is being done.

While coding, we ran issues implementing leddec display for file reading code.

Eugene compiled a GitHub to document the issues, https://github.com/EKozlakov/CPE487A-DSD/blob/master/finalProject/pinProbs.md.

Will move project to its own repository for easiness of reading and future readability.

Continued working on project

Ran into problems implementing leddec display for file reading code. Problems are described on my GitHub markdown here . Will continue to pursue other avenues regarding this project. Considering moving project to it's own repository.

Continued working on the project, not much documentation to be done. Created separate repository for the final project to keep things organized.

As we remained stuck on bug for multiple days, our team finally overcame it with the help of the professor initially, which led us on to figure it out on our own.

Instead of creating separate repository, I had decided with the team to just keep the labs done together in the team GitHub, thus making it easier and not having to load different branches and manage loads of data.

Made some progress on the project, time is narrowing down to a few weeks but it is looking like we will make the deadline.

NOT DONE YET

As we remained stuck on bug for multiple days, our team finally overcame it with the help of the professor initially, which led us on to figure it out on our own.

Instead of creating separate repository, I had decided with the team to just keep the labs done together in the team GitHub, thus making it easier and not having to load different branches and manage loads of data.

Made some progress on the project, time is narrowing down to a few weeks but it is looking like we will make the deadline.