SiliconJackets @ Georgia Tech
SiliconJackets @ Georgia Tech
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Starting in my first semester at Georgia Tech, I have been a member of SiliconJackets, a 100% student-led organization which designs and tapes-out custom chips. I am a part of the Physical Design sub team, and I helped optimize the layout of our memory module for our first tape-out. Detailed below is a brief summary of my experiences from the club, and what I have learned from this opportunity.
Memory Module Optimization
Memory Module Optimization
After officially joining the Physical Design sub team, I signed up to work on the memory module of our RISC-V core. The main goal of my work on this submodule was to optimize its power, performance, and area (PPA) characteristics.
Together with the rest of the memory module team, we worked with the design flow, adjusting parameters as we saw fit in order to achieve the best PPA characteristics. This meant adjusting the overall size of the module, for example. These dimensions define the maximum size the module will be, forcing our EDA tools to modify the physical layout of the module. This may require additional buffers or adjusting the length of certain nets to ensure accurate performance. Of course, this also affects the performance and power requirements of the module, but this was not something apparent to me before working through this experience.
Through this work, I have learned a great deal about the ideas of CPU pipelining, and how each stage affects and determines the requirements of the others. In addition to learning about the chip design process, I also became familiar with industry-standard tools like Cadence Innovus which I also used through a SSH connection into a Linux server.
Screen caps from some intermediate outputs of the design flow
Onboarding
Onboarding
As a part of the onboarding for SiliconJackets, I had to explore what it meant to be a Physical Design Engineer. Overall, the onboarding was broken up into a few different steps, and successful completion of all of them enabled me to join the club.
The first step in the onboarding process was to ensure that I had up to par Python skills. This required me to write a script to take a sample timing report of a basic chip design and find specific information. Specifically, I had to parse the data included in the report and find the net which had the worst negative slack (if it existed). It turned out that the design was fairly sound, and there was no net with negative slack. Instead, it seemed like all of the nets had fairly high positive slack, indicating that there was room for improvement in the clock speed of the chip. Thus, the next part of this script assignment was to estimate how much faster the design could be pushed.
[check for and add in documentation to show I completed this]
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