Professional Background

Sponsored Research

Membership

• IEEE Electron Device Society

• IEEE Circuit and System Society

• IEEE Nanotechnology Council

• IEEE Computer Society Technical Committee on VLSI

Teaching Engagement

PhD Supervision

      Research Scholar     Broad Area of Research           Year Since           Status

1.Saurabh Panwar Device-Circuit Interactions in Ferro-electric FETs         July 2020 Ongoing

2.Shobhit Sriwastava Reliability of Stacked Nanosheet FETs for Low Voltage Circuit Design July 2020 Ongoing

3.Shashadhara M. 2D Material for Spintronic based SOT MRAMs Jan 2021 Ongoing

Publications (Recent Past)

Journal Publications

1. Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, “A Novel VDSAT Extraction Method for Tunnel FETs and its Implication to Analog Design”, IEEE Trans. on Electron Devices, vol. 64, no. 2, pp. 629-633, Feb. 2017.

2. Abhishek Acharya, Abhishek B. Solanki, Sudeb Dasgupta and Bulusu Anand, “Drain Current Saturation in Line Tunneling based TFETs: An Analog design Perspective”, IEEE Trans. on Electron Devices, vol. 65, no. 1, pp. 322-330, Jan. 2018.

3.  Abhishek Acharya, Abhishek B. Solanki, S. Glass, Q. T. Zhao, and Bulusu Anand, “Impact of gate-source overlap on Device/Circuit Analog Performance of Line TFETs”, IEEE Trans. on Electron Devices, vol. 66, no. 9, pp. 4081-4086, Sep. 2019.

4. S. Srivastava, S. Panwar and Abhishek Acharya, "Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight," in IEEE Transactions on Electron Devices, vol. 8, Aug. 2022, doi: 10.1109/TED.2022.3184915. 

5. S. Srivastava, S. M and Abhishek Acharya, "Investigation of Self-Heating Effect in Tree-FETs by Interbridging Stacked Nanosheets: A Reliability Perspective," in IEEE Transactions on Device and Materials Reliability, vol. 23, no. 1, pp. 58-63, March 2023, doi: 10.1109/TDMR.2022.3227942. 

6. M. Shashidhara, V. Nehra, S. Srivatsava, S. Panwar and A. Acharya, "Investigation of Field-Free Switching of 2-D Material-Based Spin–Orbit Torque Magnetic Tunnel Junction," in IEEE Transactions on Electron Devices, vol. 70, no. 3, pp. 1430-1435, March 2023, doi: 10.1109/TED.2023.3237654 

7. S. Panwar, S. Srivastava, M. Shashidhara and Abhishek Acharya, "Performance Evaluation of High-κ Dielectric Ferro-Spacer Engineered Si/SiGe Hetero-Junction Line TFETs: A TCAD Approach," in IEEE Transactions on Dielectrics and Electrical Insulation, vol. 30, no. 3, pp. 1066-1071, June 2023, doi: 10.1109/TDEI.2023.3266413. 

8. M. Shashidhara , S. Srivastava, S. Panwar,  and Abhishek Acharya, " Spin-Orbit Torque Magnetic Tunnel Junction based on 2-D Materials: Impact of Bias-Layer on Device Performance", Soild State Electronics, Elsevier, August, 2023. https://doi.org/10.1016/j.sse.2023.108757 

9. S. Srivastava, S. Panwar, M. Shashidhara , S. Yadav and Abhishek Acharya, " Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective ", Soild State Electronics, Elsevier, August, 2023. 

10. S. Panwar, M. Shashidhara , S. Srivastava, D. Joshi and Abhishek Acharya, " Performance Optimization of Epitaxial-Layer Based Si/SiGe Hetero-junction Area Scaled Tunnel FET Label-Free Biosensors Considering Steric Hindrance ", Soild State Electronics, Elsevier, 2023. 

11. Abhishek Acharya “Investigation of Variability in Device Design on Saturation Characteristics of Nanowire Tunnel FETs”, Silicon, Springer, May. 2021. 

12. Atul Kumar Yadav, Sourabh Panwar, Shobhit Srivastava, and Abhishek Acharya, "Performance Analysis of III-V Hetero/Homojunction TFETs: an Analog Circuit Design Perspective", Silicon, Springer, June 2021. DOI: 10.1007/s12633-022-01889-z 

13. Awadhiya, B., Yadav, S. & Acharya, A. Interface Trap Charges Analysis on DC and High Frequency Characteristics of UTBB-FDSOI FET. Silicon (2022). https://doi.org/10.1007/s12633-022-02053-3 

Conference Publications

1. Abhishek Acharya and Aand Bulusu, "Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: a Physical Insight", in proceeding of the IEEE International Symposium on Circuits & Systems (ISCAS 2023), California, USA from May 21 - 25, 2023 .

2.  S. Srivastava, S. Panwar, M. Shashidhara, D. Joshi, N. Bagga and Abhishek Acharya, "Performance Investigation of Source/Drain Extension Region on Nanosheet FET: A Digital Design Perspective", in proceeding of the Silicon Nanoelectronics Workshop, VLSI Symposium on Technology and Circuits,  Jun. 2023, Kyoto, Japan.

3. S. Panwar, S. Srivastava, M. Shashidhara, D. Joshi, P. Dubey and Abhishek Acharya, "Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs ", in proceeding of the Silicon Nanoelectronics Workshop, VLSI Symposium on Technology and Circuits,  Jun. 2023, Kyoto, Japan.

4. M. Shashidhara , S. Srivastava, S. Panwar,  and Abhishek Acharya, " Spin-Orbit Torque Magnetic Tunnel Junction based on 2-D Materials: Impact of Bias-Layer on Device Performance", 9th International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Tarragona, Spain, 2023.

5. S. Srivastava, S. Panwar, M. Shashidhara , S. Yadav and Abhishek Acharya, " 9th International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Tarragona, Spain, 2023. 

6. S. Panwar, M. Shashidhara , S. Srivastava, D. Joshi and Abhishek Acharya, " Performance Optimization of Epitaxial-Layer Based Si/SiGe Hetero-junction Area Scaled Tunnel FET Label-Free Biosensors Considering Steric Hindrance ", 9th International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Tarragona, Spain, 2023. 

7. Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, “Impact of Device Design Parameters on VDSAT and Analog Performance of TFETs”, in proceeding of the Silicon Nanoelectronics Workshop, VLSI Symposium on Technology and Circuits, 4-5 Jun. 2017, pp. 53-54, Kyoto, Japan.

8. Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, “Understanding Drain Current Saturation and VDSAT Extraction in Tunnel FETs: Analog Design Outlook”, in PhD Forum, International Conference on VLSI Design, 6-10 Jan. 2018, Pune, India.

9. Abhishek Acharya and Bulusu Anand, “Influence of Body-Bias and Gate-Source Overlap Length on the Analog Performance of Epitaxial Layer Enabled Area Scaled Tunneling FETs”, in PhD Forum, International Conference on VLSI Design, 5-9 Jan. 2019, New Delhi, India.

10. Atul K. Yadav and Abhishek Acharya, "Investigation of III-V Tunnel FETs for Analog Circuit Design", proceeding of IEEE DevIC, May, 2021.

11. Yeswanth Chakka and Abhishek Acharya, "In memory Computing based Boolen and logical Circuit Design using 8T SRAM", proceeding of IEEE DevIC, May, 2021.

12. Manisha Mogili and Abhishek Acharya, "Design and Analysis of III-V Tunnel FET based Energy Efficient Digital Circuits", proceeding of IEEE DevIC, May, 2021.

13.  Aman K. Gupta and Abhishek Acharya, "Exploration of 9T SRAM Cell for In Memory Computing Application",  proceeding of IEEE DevIC, May, 2021.

14. C. Yeswanth, S. Panwar, S. Srivastava, D. Joshi, S. M and A. Acharya, "Configurable 8T SRAM-based Computing In- Memory Architecture for Enabling Shift Operation and Multibit Dot-Product Engines," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, 2023, pp. 330-334, doi: 10.1109/DevIC57758.2023.10134803. 

15. A. K. Gupta and A. Acharya et al., "9T SRAM Cell for Computation-In-Memory Architectures: Proposal & Investigation," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, 2023, pp. 282-286, doi: 10.1109/DevIC57758.2023.10134934. 

Book Chapter

[1]. Shashidhara M., and Abhishek Acharya, "2D Materials for Spin Orbital Torque MRAM: A path towards Neuromorphic Computing " in Emerging Low-Power Semiconductor Devices: Applications for Future Technology Nodes, CRC Press, Aug. 2022.

[2]. S. Srivastava, S. Panwar, M. Shashidhara , and Abhishek Acharya, Challenges and future scope of gate-all-around (GAA) transistors physical insights of device-circuit interactions, Device Circuit Co-Design Issues in FETs, CRC Press, Taylor & Francis Group, 2023

[3]. Abhishek Acharya, S. Panwar, S. Srivastava, M. Shashidhara, "Epitaxial Layer-Based Si/SiGe Hetero-Junction Line Tunnel FETs: A Physical Insight "  Advance Ultra Low Power Metal Oxide Semiconductor Field Effect Transistors and Their Applications, Wiley Scrivener Publishing, 2023

FDP/STTP/Workshop Conducted