Ferroelectric Devices

Ferroelectric (FE) devices based on doped-hafnium oxides (HfO2) have been reported as great candidates for low-power logic, nonvolatile memory (NVM), and in-memory computing applications due to their compatibility with CMOS technology. They have some advantages over other types of electronic devices, such as high endurance, low power consumption, and fast switching speeds. 

NCFET has been reported to overcome the fundamental limit of conventional CMOS technology (60 mV/dec). It can be used in low-power circuit applications due to the internal voltage amplification provided by the ferroelectric layer. Additionally, it can offer higher ON current and low threshold voltage compared to conventional FETs.

We have studied the device physics and modeling of these devices for designing the next-generation electronic circuits. 

• A. Kumar, M. Ehteshamuddin, A. D. Gaidhane, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Universal Compact Model of Flicker Noise in Ferroelectric Logic and Memory Transistors,” in IEEE Transactions on Electron Devices, vol. 71, no. 1, pp. 18–22, Jan. 2024.

• A. Kumar, A. Bulusu, S. Mehrotra, and A. Dasgupta, “A Landau-Based Compact Model for Multi Domain Ferroelectric Field Effect Transistors,” International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2023.

• A. Kumar, G. Pahwa, A. K. Behera, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Analysis and Modeling of Flicker Noise in Ferroelectric FinFETs,” 2022 IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, 2022, pp. 1–5.

• A. Kumar, N. Mishra, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Impact of Doped Hafnium Oxides on Memory Window and Low-Frequency Noise in Ferroelectric FETs,” in IEEE Transactions on Electron Devices, vol. 71, no. 7, pp. 4015–4020, July 2024.

• A. Kumar, S. Mehrotra, A. Bulusu, and A. Dasgupta, “Performance Projection of Gate-All-Around (GAA)-based Negative Capacitance Complementary FET (NC-CFET) Relative to Standard CFET,” in IEEE Journal of the Electron Devices Society, 2024.

• A. Kumar, A. Bulusu, and A. Dasgupta, “Performance Projection of Negative Capacitance Complementary FET (NC-CFET): Device-Circuit Co-design,” 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3.

• A. Kumar, A. Saxena, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Compact Modeling of Flicker and Thermal Noise in Ferroelectric Devices,” International Compact Modeling Conference (ICMC), San Francisco, CA, USA, 2025.

• A. Kumar, S. Mehrotra, A. Bulusu, and A. Dasgupta, “A Method to Generate Additional Volatile States Using Single-domain Ferroelectric Field-Effect Transistor,” in Journal of Applied Physics, Mar. 2025.

ULTRARAM

ULTRARAM is a non-classical charge-trapping-based emerging NVM that exhibits fast, non-volatile, high endurance (>10^7 P/E cycles), long retention (>1000 years), and ultra-low switching energy per unit area characteristics. It breaks the paradigm of the unachievable universal memory idea. Unlike a single SiO2 barrier in a flash, the novelty comes from the InAs/AlSb triple barrier resonant tunneling (TBRT) mechanism. The TBRT structure provides a high-energy electron barrier with no bias and allows fast resonant tunneling at program/erase pulse (±2.5V) with switching energy approximately ten times smaller than Flash. However, ULTRARAM is in the early stage of development and needs to overcome several challenges.

We have developed a physics-based model that captures the trapping and de-trapping of charge in the floating gate (FG) using TBRT physics and is used to calculate the device characteristics. This model can be used for circuit design with a ULTRARAM memory device.

• A. Kumar, M. Ehteshamuddin, A. Bulusu, S. Mehrotra, and A. Dasgupta, “A Physics-based Compact Model for ULTRARAM Memory Device,” 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3.

• A. Kumar and A. Dasgupta, “Compact Modeling of Compound Semiconductor Memory ULTRARAM: A Universal Memory Device,” 2024 Device Research Conference (DRC), College Park, MD, USA, 2024, pp. 1-2.

ML for EDA

Machine learning (ML) is revolutionizing Electronic Design Automation (EDA) by improving efficiency, accuracy, and scalability in the design and optimization of electronic systems. Both foundries and design companies rely on EDA to support their businesses. A key component in EDA that bridges the foundry technology and IC design is device compact models. ML models, such as neural networks and reinforcement learning, reduce simulation overhead, automate repetitive tasks, and provide predictive insights into design metrics. Additionally, ML-assisted algorithms can be used to optimize advanced node semiconductor devices. There are many ways to optimize two or more target objectives. On the one hand, we have TCAD-based optimization, which is a trial-and-error method and requires experience and a deep understanding of device physics. Contrary to this, the other method is a framework that utilizes an ML-assisted genetic algorithm to maximize or minimize the value of target objectives.

• M. Ehteshamuddin, A. Kumar, S. Roy, and A. Dasgupta, “Optimizing Memory Window and Polarization of a Fe-CAP Using Machine Leaning Assisted Genetic Algorithm Framework,” International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2023.

Ph.D. Course Work

1) NANO SCALE DEVICES (ECN-587)                                                                  

2) FOUNDATIONS OF SEMICONDUCTOR DEVICE PHYSICS (ECN-579)                                       

3) VLSI TECHNOLOGY (ECN-577)                                                  

4) DIGITAL VLSI CIRCUIT DESIGN (ECN-573)                                                                              

5) ANALOG VLSI CIRCUIT DESIGN (ECN-581)                                                              

6) COMPACT MODELING OF SEMICONDUCTOR DEVICES (ECN-561)                                  

7) MAGNETIC RANDOM-ACCESS MEMORY (ECN-635)