Embedded Files
LAYOUT
LAYOUT
This is the complete layout of the 16 bit microprocessor which consists of the register file and the data-path. It is designed in 45nm technology using Virtuoso.
TOP LEVEL BLOCK DIAGRAM
TOP LEVEL BLOCK DIAGRAM
This is the top level view of the microprocessor consisting of the register file, the data-path and the control.
The register file and the data-path was designed in Virtuoso and the control logic was described using Verilog (Hardware Description Language), the two were co-simulated to test the entire design. The Assembly files used custom 16-bit instructions and were assembled using a provided code that converted the assembly into control signals based on the control logic defined by the Verilog file.
DATAPATH
DATAPATH
This is the data-path section of the processor, the instructions supported are ADD, AND with LSB, Right Shift and Left Shift. The combination of these instructions are used to perform an iterative multiply. These operations are performed on all data coming out of the register file and the results are multiplexed to form a single output which is chosen on the basis of the instruction. The output gets latched to be sent back to the register file.
REGISTER FILE
REGISTER FILE
This is the register file section. The register file can store 16 16-bit registers. It supports LOAD and STORE instructions. There are two read ports and a single write port in the register file. The data gets latched onto the buses going to the data-path after passing through the FlipFlops.
FLOOR PLAN
FLOOR PLAN
This the floor-plan of the layout , its the rotated version of the layout shown above. The dimensions shown are in micrometers. The total area of the layout came out to 2117.6 umsq.
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