Title: Error-bounded Lossy Compression for Accelerators 

Abstract: With the rapid development and deployment of emerging accelerators—such as modern GPU architectures and specialized systems like Cerebras—scientific applications and AI models are increasingly leveraging these platforms to achieve unprecedented performance. In this talk, I will present the significant efforts of the SZ team in developing and optimizing error-bounded lossy compression techniques tailored for accelerator-based computing. In particular, I will introduce two key libraries: cuSZp, designed for CUDA-enabled GPUs, and CereSZ/WaferSZ, developed specifically for the Cerebras architecture. I will first discuss the background and motivation behind accelerator-oriented compression, and then highlight the core design principles and performance optimization strategies used in our implementations. The work presented in this talk has been published in top-tier conferences, including SC23, SC24, SC25, HPDC24, IPDPS25, and others.

Title: Argonne Project Update and PCA-Based Compressor Design in Chisel 

Abstract: I will first cover Argonne's ongoing projects and then discuss a Principal Component Analysis (PCA)-based compressor design implemented in Chisel. PCA-based compression is an effective technique for compressing X-ray detector data and has been shown by several research groups to achieve high compression efficiency in simulation. However, practical deployment in digital hardware remains challenging due to the large-scale vector–matrix multiplications required. Implementing PCA using single-precision floating-point arithmetic is prohibitive in terms of logic area and performance. In this work, we propose a hardware-oriented PCA compressor design based on integer quantization of PCA weights and an efficient

tree-structured reduction architecture. The design is implemented in Chisel, enabling scalable and parameterizable generation of the compression logic while maintaining compression effectiveness and hardware efficiency. 

Title: Designing Custom RoCC Hardware Accelerators in Chipyard for Streaming Compression

Abstract: Modern scientific instruments are rapidly approaching regimes where detectors produce terabytes of data per second, making data movement—not computation—the primary performance bottleneck. Streaming, error-bounded lossy compressors such as SZx/SZxp can significantly reduce data volume, but software implementations alone struggle to keep pace with emerging bandwidth demands. This talk presents a step towards reusable framework for custom RoCC-based hardware accelerators in the Chipyard RISC-V ecosystem, using SZx as a concrete case study.

I will show how we mirror a software compressor into Chisel as a modular block processor, and how Chipyard’s RoCC co-processor interface lets us separate a generic interface shell (command, data, memory, response paths) from a pluggable compression core integrated into a Rocket-based SoC. I will conclude with a live Chipyard demo and future directions toward a “plug-and-play” framework where alternative compressors (e.g., SZ, ZFP, lossless codecs) can reuse the same RoCC shell for rapid evaluation.

Title: Introduction of 3D-stacking LSI system project in Kumamoto