Parallel In Serial Out Shift Register Circuit
A parallel in serial out shift register can be constructed by using D flip-flops, which are basic memory elements that can store one bit of data. The D flip-flops are connected in a chain, such that the output of one flip-flop is connected to the input of the next one. The parallel inputs are connected to the D inputs of each flip-flop, and the serial output is taken from the Q output of the last flip-flop. The following figure shows a four-bit parallel in serial out shift register circuit.
The operation of the parallel in serial out shift register is as follows:
When the clock signal is low, the data at the parallel inputs are stored in the D flip-flops, but they do not appear at the Q outputs yet.
When the clock signal rises from low to high, the data at the D inputs are transferred to the Q outputs simultaneously. This is called loading or parallel transfer.
After loading, the data at the Q outputs are shifted to the right by one bit for each clock cycle. This is called shifting or serial transfer.
The shifting continues until all the data bits are shifted out from the serial output.
Parallel In Serial Out Shift Register VHDL Code
VHDL is a hardware description language that can be used to design and simulate digital circuits. VHDL code for a parallel in serial out shift register can be written by using a generic parameter to specify the number of bits, and a for loop to instantiate the D flip-flops. The following is an example of VHDL code for a four-bit parallel in serial out shift register.
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library ieee; use ieee.std_logic_1164.all; entity piso is generic (n: integer := 4); -- number of bits port ( clk: in std_logic; -- clock signal rst: in std_logic; -- reset signal din: in std_logic_vector(n-1 downto 0); -- parallel input dout: out std_logic -- serial output ); end piso; architecture behav of piso is component dff is -- D flip-flop component port ( d: in std_logic; -- data input clk: in std_logic; -- clock input rst: in std_logic; -- reset input q: out std_logic -- data output ); end component; signal reg: std_logic_vector(n-1 downto 0); -- internal register signal begin gen: for i in 0 to n-1 generate -- for loop to generate D flip-flops ff: dff port map ( -- instantiate D flip-flop d => din(i), -- connect parallel input to D input clk => clk, -- connect clock signal to clock input rst => rst, -- connect reset signal to reset input q => reg(i) -- connect Q output to register signal ); end generate; dout '0'); -- clear register signal else -- if reset is low reg
References
The following sources were used to create this article:
[VHDL Code for 4-Bit Shift Register - Invent Logics]
[Vhdl Parallel or Serial-in/ Parallel-out register - Stack Overflow]
[n bit shift register (Serial Out) in VHDL - Electrical Engineering Stack Exchange]
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