CMOS VLSI Design

CMPE 640 - Custom VLSI Design[3]This course introduces the CMOS VLSI design process and focuses on design at the circuit and physical levels. Students design, implement, fabricate and test basic logic gates and other VLSI structures such as adders and multipliers using computeraided design tools and laboratory test and measurement equipment. Basic layout and simulation techniques are covered in addition to CMOS processing technology, MOS transistor theory, performance estimation, CMOS design styles, VLSI structures and timing issues. The Verilog hardware description language is used in the laboratories.

An introduction to most aspects of large-scale MOS integrated circuit design including: device fabrication and modeling; inverter characteristics; designing CMOS combinational and sequential circuits; designing arithmetic building blocks and memory structures; interconnect and timing issues; testing and verification; and system design considerations. Term projects involve the complete design of a functional logic block or system using CAD tools.

CMOS VLSI Design

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Data analysis, storage and communication has become a very important subject for research nowadays. Due to higher demand for data, power and area reduction have drawn more attention in recent research. In this dissertation we propose new system for data communication through optical links which is area and power efficient while maintaining high performance. We also propose a new approach for biosensing which also focuses on area and power efficiency with improved performance which enables analyzing huge amounts of data.In the first part of this dissertation, a 1Tb/s transceiver system is introduced. This system is designed for microring resonator links. Therefore, a control loop design is also introduced in this part for wavelength locking. Two versions of the 1Tb/s transceiver with less than 90fJ/bit energy efficiency is implemented in 22nm FDSOI to achieve 5Tbit/(mm2) and 0.8Tbit/(mm2) densities. New system and circuit designs are proposed to achieve such low power and density at 1Tb/s. A closed loop wavelength locking control loop is also proposed consuming low power and area while locking the rings in less than 25\u00B5s. A 20 channel wavelength locking system is implemented in TSMC 65nm.\nIn the second part of this dissertation, we introduce biological sensors and sensor interfaces for biological applications. Nanopore sensors enable a wide range of sensors from DNA sequencing to polymer mass spectrometry by exploiting the resistive pulse technique. The small and high-speed sensor signal can make the electronics design challenging. The designer is often faced with a bewildering choice of architectures and circuit topologies. In this part, we review the most prominent circuits and architectures used in nanopore sensing highlighting the advantages and disadvantages of each approach. Additionally, noise analysis and SNR calculations are shown for each topology. We also provide a graphical method to allow the designer to narrow down their choice for a given set of requirements. As the need for large sensor arrays is continually increasing, we discuss the different approaches to scaling the system when using an array of sensors. We also introduce the system design of a new high precision potentiostat. Our direct current-to-digital conversion is capable of sensing picoampere (pA) currents without a need for transimpedance amplifiers (TIAs). Our idea utilizes a \u2206\u03A3 modulator with one very important difference, current feedback via slope scaling. This feature allows us to utilize noiseless elements such as capacitors in the feedback loop to achieve high performance. We have validated the system using both theory and experiment. Performance improvement over current systems is first demonstrated by performing a theoretical analysis of the expected noise of the system. A 10\u00D710 cm2 PCB prototype was fabricated as a proof of concept. The slope scaling idea is applied to both first and second order \u2206\u03A3 Analog to Digital Converters (ADCs) with signal input bandwidth of 1.57 KHz with an oversampling ratio of 64. Signal-to-Noise-and-Distortion Ratio (SNDR) of 40 dB and 60 dB is achieved with 1st and 2nd order \u2206\u03A3 ADCs, respectively. The noise floor of the implemented circuit is 569 fA over a 1KHz bandwidth and was tested for input currents ranging from 100 pA to 1 \u00B5A. In this part, we also propose a direct current to digital 125\u00B5W, area efficient (0.042mm2) 81dB DR, 8KS/s current sensing ADC implemented in 45nm CMOS capable of sensing sub-pA currents. Our approach combines the TIA and ADC into a unified structure by folding a low-noise capacitive TIA into the first stage integrator of a 2nd order Delta-Sigma (\u2206\u03A3) modulator. We mitigate the common issue of feedback DAC noise faced by current sensing \u2206\u03A3 converters by using a low-noise current scaling technique. In our approach an integrator-differentiator pair scales the DAC feedback current using capacitors. Since the DAC is current based the integrator is simply a charge-pump, alleviating the bandwidth issues arising from the periodic reset required by the integrator. However, the periodic reset forces the converter to operate in an incremental mode lowering the dynamic range of the converter. We overcome this by using a floating correlated double sampling (CDS) technique. The correlated double sampling also enables the use of single stage common source amplifiers while achieving a high-gain resulting in a low-power area-efficient design.

Low-power VLSI circuit design is a dynamic research area driven by the growing reliance on battery-powered portable computing and wireless communications products. In addition, it has become critical to the continued progress of high-performance and reliable microelectronic systems. This self-contained volume clearly introduces each topic, incorporates dozens of illustrations, and concludes chapters with summaries and references. VLSI circuit and CAD engineers as well as researchers in universities and industry will find ample information on tools and techniques for design and optimization of low-power electronic systems. Topics include:

Changes have been made throughout each chapter to cover the latest practical developments in chip design. Four new chapters: Delay; Power; Interconnect; and Robustness (Chapters 4-7). Previously, this material was covered in one chapter. Power consumption is introduced in Chapter 1, covered in depth in Chapter 5, and woven throughout the text as an equal partner to performance. Emphasis is on practical techniques used on commercial chips. Expanded coverage of clocking and I/O circuits used in modern systems. The VHDL and Verilog appendices are combined to offer side-by-side coverage of the two languages. SystemVerilog, the leading language for verification, is also introduced. The Table of Contents is reorganized to more closely follow a typical course syllabus Short biographies and photographs of influential figures in the semiconductor world Chapter-length case study (Chapter 15) of the design of a commercial system-on-chip in a modern process, illustrating the practical methods and issues faced by designers. Circuit examples have been updated from 180 nm to 65 nm Available packaged with Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, a hands-on lab manual. To order this package, use ISBN: 0137060815.

The book presents a comprehensive introduction to custom VLSI design in the complementary MOS (CMOS) technologies and contains a large number of practical design examples. Topics discussed include CMOS circuits, MOS transistor theory, CMOS processing technology, circuit characterization and performance estimation, and CMOS circuit and logic design. The discussion also covers structured design and testing, symbolic layout systems, and CMOS subsystem design.

VLSI and nanocomputing has become the most desirable feature of any integrated chip. Computers are also becoming more portable. ICs are being introduced everywhere. This huge implementation of IC has also opened a scope of research. Size of IC has become an issue to think about. Power dissipation is also another important consideration as performance of VLSI chip design. Low-power high-speed CMOS circuit design methodologies will be elaborated in this paper.

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18Âµm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

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