許大山博士 ｜聯發創新研究基地負責人 

The hardware industry is at a crossroads. There is a growing desire to shift the engineer's focus from the "How" (manual RTL implementation) to the "What" (system intent and architecture). However, this transition is currently constrained by a lack of expertise in intent-based engineering, opaque and waterfall toolchains, and a heavy reliance on accumulated unexplained code optimizations. While "Spec-to-RTL" AI tools have optimized the "printing" of logic, they have also exposed a new bottleneck: the immense difficulty of writing a rigorous, verifiable specification that actually works and optimizes design goals.

This talk introduces a practicable paradigm shift: Incremental Test-Driven Development (TDD) for the IC Specification. We propose that a "good" specification is defined by its ability to predictably drive a toolchain to generate the desired RTL and verification artifacts. We utilize an experimental AI Agent to bridge the gap between human intent and the infrastructure of truth—automating the generation of test benches, assertions, and pattern discovery, so verification is not only “shift lef” but a first-class citizen of IC design.

By adopting a "Test (the spec) first, Code (the spec) later" approach, designers apply SDD-TDD principles across the entire design cycle. This enables the incremental and observation-based adjustment of both mandatory behavioral requirements and architectural optimizations within a single, unified verification loop that guarantees the spec is perfectly matched to the generation toolchain. To demonstrate this workflow, we will walk through an example complex hardware design process, showing how an architect of intent can navigate a design backlog to arrive at a robust spec and hence an optimized design.