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Master's Student | Electrical and Computer Engineering
University of Michigan, Ann Arbor
Interest Keywords:
Hardware Acceleration Architecture/Computer Architecture/VLSI Design
See additional info in the [bio] page.
Skill Sets
Digital Design/Verification
Synopsys VCS/DVE
Synopsys VC-Formal
Programming
Verilog / Systemverilog / SVA
C++
Python
Languages
English (Proficient)
Traditional Chinese (Native)
Tools
Linux (Bash)
Vim
Tmux
Git
Latex (Overleaf)
Past Projects / Research Experience
Synopsys Formal Verification Internship
Synopsys Taiwan @ Hsinchu, Taiwan
2021/06 - 2021/08
Verify part of the Synopsys machine leaning accelerator IP using formal verification methodologies and VC-Formal.
Assistance in verification and post-APR simulation for chip tape-out
MICL Laboratory @ University of Michigan, Ann Arbor
2021/05 - Present
PI: Professor David Blaauw, PhD
Supervisor: Mehdi Saligane, PhD
Added SPI/UART functionality and provided post-synthesis verification foundations for the GF12 and skywater 130 nm chip tape-out using OpenROAD. Written bash scripts to automate regression testing multiple clock frequencies.
Tools used in the project:
Synopsys VCS/DVE
Synopsys Design Compiler
Primetime
2 Way Superscalar Out-of-Order R10K Microprocessor
EECS 470 Computer Architecture Final Project @ University of Michigan, Ann Arbor
2021/02 - 2021/04
Our team designed a 2-Way Superscalar Out-of-Order R10K Microprocessor with store-to-load forwarding, 2-way set-associative caches, prefetching instruction cache and bi-modal branch predictor using Systemverilog.
This project has been synthesized with a 9ns clock using DC from Synopsys.
Tools used in the project:
Synopsys VCS/DVE
Design Compiler
Component Labeler using VLSI CAD Design Tools
CVSD Final Project @ National Taiwan University, Taipei
2020/12 - 2021/01
Designed a 2-scan component labeling engine with the use of Synopsys and Cadence EDA tools.
This project has been synthesized and P&Red successfully.
See more in Github.
Tools used in the project:
Cadence ncverilog
Design Compiler
Cadence Innovus
Studies in Deep Learning Accelerator Dataflow
Short Term Research Internship @ Delta Electronics, Taipei
2020/06 - 2020/08
PI: Jeff Tsai, Principal Engineer
Read about novel architecture and analysis techniques listed below:
Eyeriss v2, a Row Stationary architecture design by Yu-Hsin Chen
Hardware constraint analysis and an Output Stationary design by Yu-Fei Ma
MAESTRO Data-directive-driven Simulation Platform by Georgia Tech Synergy Lab
Performed a quantitative analysis of various dataflow schemes and its performance implications using the MAESTRO simulator
Basic Design of a Reconfigurable Digital Neuromorphic Architecture
Research Internship @ UC San Diego
2019/06 - 2019/08
PI: Gert Cauwenberghs, Ph.D
Special Thanks to: Bruno Pedroni, Ph.D
This is a basic architecture designed to speed up the inference of ANNs. Future work may include extending functionality such as training capabilities and pipeline optimization.
See code and presentation here.
Machine Learning Approaches for Predicting and Analyzing the Drying Process in the Textile Industry
Research Assistant @ National Central University, Taiwan
PI: Wen-June Wang, Ph.D
This is a conference proceeding published in CACS 2019. See abstract below.
The main objective of this paper is to establish an output/input relationship model based on machine learning for the fabric drying process of a general textile factory. The scenario of the fabric drying process involves a conveyor belt that drives the fabric through eight drying boxes, and the targeted metric of the post-drying fabric is the moisture content rate.
See full text here.
Autonomous Vehicle via Digital Logic Course Project
Summer Exchange Program @ Hong Kong University of Science and Technology
2017/06 - 2017/08
In this project, we made an autonomous vehicle, which can identify and move along the white lines in the green background by itself by utilizing sensors and different logic ICs. The vehicle we made should also make right decisions on which direction to go when facing Y-splits and moving back when encountering a white wall.
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