12-08-2020: Filled out course survey and updated some of the documentation for my group's Brick Breaker project.
12-01-2020: Further programmed the bricks using VHDL with my FPGA group and worked on documenting our work and results. The bricks now break on impact and the game is functionally complete. All of the code can be found on Anisha's GitHub repo under "Final Project". All of our documentation can be found on this Google webpage.
11-24-2020: Worked with my group to program the bricks in our Brick Breaker game in VHDL. The bricks are drawn onscreen but do not yet break when hit with the ball. We are close to having a working result now.
11-17-2020: Met with my FPGA group to further discuss how we could build our game. We spent much of the time looking at other Brick Breaker FPGA projects we could find and comparing them to what we are trying to achieve. Some of the code is useful but much of what is out there is written in different languages for different hardware.
11-10-2020: Met with my FPGA group and discussed possible methods of building our game. We mainly looked at the Pong code for Lab 6 and discussed how many of the elements in Pong, such as the ball and movable paddle, could be used or tweaked slightly to work in our Brick Breaker game.
11-03-2020: Finished the final FPGA lab, Lab 6: Video Game PONG; decided with group on final project: an FPGA "Brick Breaker" game
10-27-2020: Worked on FPGA Lab 4: Hex Calculator and FPGA Lab 5: DAC Siren
10-20-2020: Worked on FPGA Lab 2: Four-Digit Hex Counter and FPGA Lab 3: Bouncing Ball
Contribution: "BCD to 7 Segment LED Display Decoder Circuit" by electronicshub.org. Helpful explanation and interesting diagrams of the 7 Segment Decoder I found while working on Lab 1.
10-13-2020: Met with FPGA group and worked on FPGA Lab 1: Seven-Segment Decoder
10-06-2020: Installed Vivado; Discussed VHDL data objects, electronic design automation, for and while loops, and standard digital circuits; read textbook chapters 11, 12, and 13
09-29-2020: Discussed Structural Modeling and modularity in VHDL, registers, and the register transfer level; read textbook chapters 9 and 10
09-22-2020: Joined a group for the FPGA project; discussed VHDL operators, memory, finite state machines, behavioral models, and one-hot encoding; read textbook chapters 6, 7, and 8
09-15-2020: Completed hello, half adder, and full adder examples in GHDL; discussed the data-flow and behavioral approaches to architecture, process statements and sequential statements; read textbook chapters 4 and 5
09-08-2020: Installed and tested GHDL and GTKWave; discussed black box, entities, architecture, in/out, data-flow models, and objects; read textbook chapters 2 and 3
09-01-2020: Created google site and GitHub repository; reviewed and discussed syllabus; read textbook chapter 1