Patrick Biesty

My Info

Patrick Biesty

Email: Pbiesty@stevens.edu

GitHub: https://github.com/Pbiesty

GitHub Repo: https://github.com/Pbiesty/CPE487

Computer Engineering '22

Understanding VHDL

VHDL - Very High Speed Integrated Circuit Hardware Description Language

Concurrent Language

Breaking down VHDL code and black-box above

Each port name is unique and has an associated mode and data type. This is a requirement.
The VHDL compiler allows several port names to be included on a single line. Port names are separated by commas. Always strive for readability.
Port names are somewhat lined up in a feeble attempt to increase readability. This is not a requirement but you should always be striving for readability. Remember that white spaces are ignored by the compiler.
A comment, which tells us what this this entity does, is included.
A black-box diagram of the circuit is also provided. Once again, drawing some type of diagram helps with any VHDL code that you may be writing. Remember: do not be scared, draw a picture

WEEK 1

Created this website! Began reading Free Range VHDL

Bundle

Bundle is used to describe multiple signals with a similar purpose.

This black box uses a slash-and-number notation

The slash across the signal line indicates the signal is a bundle and the associated number specifies the number of signals in the bundle.

WEEK 2

Downloaded GHDL http://ghdl.free.fr/download.html

Practiced with basic code (Half adder, Hello world, etc.)

Got familiar with GHDL commands on cmd (half adder file as example) ->

dir //directory
ghdl -s ha.vhdl //check code for errors
ghdl -a ha_tb.vhdl //analyze files (make sure to run this command on both files)
ghdl -e ha_tb //elaborate will build executable
ghdl -r ha_tb //run file
ghdl -r ha_tb --vcd=ha.vcd //run code through testbench
gtkwave ha.vcd //run to see GTKWave and produce a wave graph

Half adder

By running a process to test every '0' & '1' value for our inputs, you can see by the GTKWave the correct Half Adder outputs.

Being familiar with using ghdl through the command prompt is important.

WEEK 3

Joined DSD Gang (Julia Chung, Matt Ross, Jake Foglia, James Parisi, Patrick Biesty, Ronald Rupert, Sean Melone) for the lab group

Started working with more complex black box and code.

Experimented making Full Adder on my own... was successful!

Full Adder Code (fa.vhdl & fa_tb.vhdl)

Full adder

WEEK 4 - 5

Continued practice with GHDL and GTKWave

Studied FPGA Basics -- A Look Under the Hood recommended buy Julia Chung to study FPGA basics.

Sharpening your VHDL code

WEEK 6

Finished last few chapters of Free Range VHDL

Clocking & Routing

You’ll likely use an external oscillator and feed it into clocking resources that can multiply, divide, and provide phase-shifted versions of your clock to various parts of the FPGA.

Routing resources not only route your clock to various parts of the FPGA, but also your data.

WEEK 7

Picked up NEXYS A7 board from Prof. Lu

This Reference Manual for the board is extremely helpful!

Finished Lab1: Seven Segment Decoder. The results are below! Pay close attention to the switches on the bottom right, because each one corresponded to a 4-bit data sequence, thus making it possible to count from 0-9 and even through letters A-F! Check out the numbers below.

NEXYS A7 Board Beginnings

WEEK 8-9

Finished Lab 2: Hex Counter

Began working on Lab 3: Bouncing Ball Lab. It was during this lab I got to really understand the hierarchy importance. The reason for this is because it contained multiple sources files to handle separate components. Starting with top module, remember the order of the code in your sources is important.

Hierarchy Importance

Check out the hierarchy for Lab 3. It can also be found on my GitHub here. Its important to understand adopting a more hierarchical design approach it is possible to reuse common elements, and segment a complex design into smaller pieces. Both of these techniques result in a more maintainable design. VHDL allows you to define and describe an 'entity', which can then be included into other, higher-level designs.

WEEK 10

Worked with my DSD team to develop our remake of the original Space Invaders Game. You can check out our process and the completed project on our team site. Our goal is to recreate the original Space Invaders with a few creative changes of our own (color change, score counter, & powerups) implemented on the Nexys A7 board.

Completed Lab 4 Hex Calculator

Lab 5 DAC Siren

This lab was implemented on our Nexys A7 board using a PMOD. After getting the basic Digital to Analog waveform working, I was able to modify it to generate different waveforms at different speeds. This channel does a great job of explaining what a DAC is.

WEEK 11

Continued with my DSD team to develop our remake of the original Space Invaders Game.

WEEK 12-14

Completed all modifications and completed our Space Invaders remake. Check out our Project Site! All further updates for the project and class will be located there!

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CPE-487