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Thank you for taking an interest in my profile. I am Zarrin Tasnim Sworna from Dhaka, Bangladesh. Currently, I am a Lecturer at Department of Computer Science & EngineeringUniversity of Dhaka (DU). Before that I was a lecturer at Department of Computer Science & Engineering of United International University (UIU), Bangladesh. I have completed my Master of Science (M.S.) and Bachelor of Science (B.Sc) from  Department of Computer Science and Engineering, University of Dhaka. I love teaching since all the curious minds make me more motivated. Even if I am upset, just a glimpse of the happy faces of my students in the class make me smile instantly. 

I am very much passionate about research. I am working in the VLSI research group since December 2013. My research interests include Human Computer Interaction, Artificial Intelligence, Machine Learning and VLSI design and . The primary focus of my current research is on algorithm design for logic synthesis, field programmable gate array (fpga) design and reversible computing. I was awarded Fellowship from the Ministry of Information and Communication Technology of Peoples Republic of Bangladesh under the program of ‘Higher Studies and Research’.
                                                                                                                              

Recent News:
  • December, 2018Video slide of our paper on "High-Speed and Area-Effcient LUT-Based BCD Multiplier Design" is presented in 4th IEEE WIECON-ECE 2018 ConferencePattaya, Thailand.
  • October, 2018: A paper "A Fast FPGA-Based BCDAdder" has been accepted in Circuits, Systems, and Signal Processing (CSSP), Springer, New York, United States.
  • September, 2018: Video slide of our paper on "An FPGA-Based Divider Circuit Using Simulated Annealing Algorithm" is presented in 18th International Symposium on Communications and Information Technologies (ISCIT2018), Bangkok, Thailand.
  • November, 2018: Paper on "A Cost-Efficient LUT-Based BCD Adder Design" has been presented in IEEE Future Technologies Conference (FTC) 2017Vancouver, BC, Canada.
  • October, 2017: Invited to submit an extended version of our ISVLSI 2017 paper in the Special issue on Recent Advances in Engineering Systems organized by Advances in Science, Technology and Engineering Systems Journal (ASTESJ).
  • August, 2017: Judge of the competitive events of the DUSS Science Festival 2017 organized by Dhaka University Science Society (DUSS).
  • July, 2017: Video slide of our paper on "An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem" is presented in ISVLSI 2017, Bochum, Germany 
  • June, 2017: Volunteered as a Paper reviewer of the journal  Microprocessors and Microsystems
  • April, 2017: Our paper on "A Cost-Efficient LUT-Based BCD Adder Design" is accepted at the FTC 2017, Vancouver, Canada
  • April, 2017:  Volunteered as a Paper reviewer of the conference ISVLSI 2017
  • March, 2017: Poster presentation of the M.S. thesis work in CSE department, Dhaka University.
  • July, 2016: Volunteered as a Paper reviewer of Microelectronics Journal
  • May, 2016: Lafifa Jamal presented our paper on "A LUT-based matrix multiplication using neural networks" in ISCAS 2016, Montreal, Canada
  • January, 2016: Mubin Ul Haque presented our paper on "An Improved Design of a Reversible Fault Tolerant LUT-based FPGA" in VLSID 2016, India