Yusaku Kaneta

Email

  • yusaku.kaneta (at) rakuten.com
  • y-kaneta (at) ist.hokudai.ac.jp

Affiliation

Research interests

  • Design of efficient data structures and algorithms (especially based on word-level parallelism).
  • Implementation of efficient data structures and algorithms.
  • FPGA implementation of efficient algorithms and data structures,

Publications

Journal papers (refereed)

  • Constant Time Enumeration of Subtrees with Exactly k Nodes in a Tree, Kunihiro Wasa, Yusaku Kaneta, Takeaki Uno, and Hiroki Arimura, IEICE Transactions on Information and Systems, Vol. E97-D, No. 3, 2014.
  • Faster Bit-Parallel Algorithms for Unordered Pseudo-Tree Matching and Tree Homeomorphism, Yusaku Kaneta, Hiroki Arimura, and Rajeev Raman, Journal of Discrete Algorithms, Elsevier, 2012.
  • A Dynamically Reconfigurable FPGA-based Pattern Matching Architecture for Subclasses of Regular Expressions, Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, and Yoshikazu Miyanaga, IEICE Transactions on Information and Systems, Vol. E95-D, No. 7, 2012.

Conference papers (refereed)

  • Fast Wavelet Tree Construction in Practice, Yusaku Kaneta, In Proceedings of the 25th International Symposium on String Processing and Information Retrieval (SPIRE 2018), Lecture Notes in Computer Science, vol. 11147, pp. 218--232, Springer, Lima, Peru, 2018.
  • Faster Practical Block Compression for Rank/Select Dictionaries, Yusaku Kaneta, In Proceedings of the 24th International Symposium on String Processing and Information Retrieval (SPIRE 2017), Lecture Notes in Computer Science, vol. 10508, pp. 234--240, Springer, Palermo, Italy, 2017. [slide]
  • Constant Time Enumeration of Bounded-Size Subtrees in Trees and Its Application, Kunihiro Wasa, Yusaku Kaneta, Takeaki Uno, and Hiroki Arimura, In Proceedings of the 18th Annual International Computing and Combinatorics Conference (COCOON 2012), Lecture Notes in Computer Science, vol. 7434, pp. 347--359, Springer, Sydney, Australia, 2012.
  • Dynamic Reconfigurable Bit-Parallel Architecture for Large-Scale Regular Expression Matching, Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, and Yoshikazu Miyanaga, In Proceedings of the 2010 International Conference on Field-Programmable Technology (FPT 2010), IEEE, pp. 21--28, Beijing, China, 2010. (Nominated for Best Paper Candidates)
  • Fast Bit-Parallel Matching for Network and Regular Expressions, Yusaku Kaneta, Shin-ichi Minato, and Hiroki Arimura, In Proceedings of the 17th Symposium on String Processing and Information Retrieval (SPIRE 2010), Lecture Notes in Computer Science, vol. 6393, pp. 372-384, Springer, Los Cabos, Mexico, 2010. [errata]
  • Faster Bit-Parallel Algorithms for Unordered Pseudo-Tree Matching and Tree Homeomorphism, Yusaku Kaneta and Hiroki Arimura, In Proceedings of the 21st International Workshop on Combinatorial Algorithms (IWOCA 2010), Lecture Notes in Computer Science, vol. 6460, pp. 68--81, Springer, London, UK, 2010.

Talks and conference papers (not refereed)

  • Recent Results on Word-RAM algorithms in Rakuten, Yusaku Kaneta, ERATO ALSIP Special Seminar 2014, Kyoto, Japan, 2014/12.
  • Broadword Implementation of Excess Search for Parenthesis Queries, Yusaku Kaneta, The 4th International Workshop on Algorithms for Large-Scale Information Processing in Knowledge Discovery (ALSIP 2014) in conjunction with PAKDD 2014, Tainan, Taiwan, 2014/05.
  • Constant Time Enumeration of Bounded-Sized Subtrees in Trees Based on Reverse Search, Kunihiro Wasa, Yusaku Kaneta, Takeaki Uno, and Hiroki Arimura, In Proceedings of the 15th Japan-Korea Joint Workshop on Algorithms and Computation (WAAC 2012), Tokyo, Japan, 2012.
  • High-speed String and Regular Expression Matching on FPGA, Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, and Hiroki Arimura, In Proceedings of the Asia-Pacific Signal and Information Processing Association 2011 Annual Summit and Conference (APSIPA ASC 2011), Xi'an China, 2011.
  • Fast String Matching Hardwares Based on Bit-Parallel Method for Data Streams, Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, and Yoshikazu Miyanaga, In Proceedings of the 2011 International Symposium on Multimedia and Communication Technology (ISMAC 2011), GCOE-RA Special Session on Advances in VLSI/FPGA Technologies, Sapporo, Japan, 2011.
  • Dynamic Reconfigurable Architecture on FPGA for Large-Scale Regular Expression Matching, Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, and Yoshikazu Miyanaga, In Proceedings of the 4th International Symposium on Global COE Program of Center for Next Generation Information Technology Based on Knowledge Discovery and Knowledge Federation, Sapporo, Japan, 2011.
  • Large-scale Pattern Matching on Reconfigurable Hardware, Yusaku Kaneta and Hiroki Arimura, The 5th Workshop on Compression, Text, and Algorithm (WCTA 2010) in conjunction with SPIRE 2010, Los Cabos, Mexico, 2010/10.
  • An FPGA-Based Stream Processing System for Efficient Multiple Regular Expression Matching, Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, and Yoshikazu Miyanaga, In Proceedings of the 2010 Interenational Symposium on Global COE Program of Center for Next Generation Information Technology based on Knowledge Discovery and Knowledge Federation, Sapporo, Japan, 2010.
  • A Data Stream Processing System for a Multiple Regular Expression Matching using FPGA, Shin-ichi Minato and Yusaku Kaneta, Panel Session "Hardware Software Co-research for Efficient Information Processing," Abstract of the Asia-Pacific Signal and Information Processing Association 2009 Annual Summit and Conference (APSIPA ASC 2009), Sapporo, Japan, 2009.
  • A Fast String Matching Algorithm and Its FPGA Design for High-Speed Stream Processing, Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, and Yoshikazu Miyanaga, Student Debate Session, PHAROS Summer School, Como, Italy, 2009.

Preprints

  • Fast Bit-Parallel Matching for Network and Regular Expressions, Yusaku Kaneta, Shin-ichi Minato, and Hiroki Arimura, Technical Report TCS-TR-A-10-47, Hokkaido University, Division of Computer Science, 2010/11. [pdf] (accepted for SPIRE 2010)
  • Dynamic Reconfigurable Bit-Parallel Architecture for Large-Scale Regular Expression Matching, Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, and Yoshikazu Miyanaga, Technical Report TCS-TR-A-10-45, Hokkaido University, Division of Computer Science, 2010/06. [pdf] (accepted for FPT 2010)
  • Faster Bit-Parallel Algorithms for Unordered Pseudo-Tree Matching and Tree Homeomorphism, Yusaku Kaneta and Hiroki Arimura, Technical Report TCS-TR-A-10-43, Hokkaido University, Division of Computer Science, 2010/05. [pdf] (accepted for IWOCA 2010)
  • An Efficient Matching Algorithm for Acyclic Regular Expressions with Bounded Depth, Yusaku Kaneta, Shin-ichi Minato, and Hiroki Arimura, Technical Report TCS-TR-A-10-40, Hokkaido University, Division of Computer Science, 2010/02. [pdf]

Others

Academic activities

  • Reviewers: WALCOM 2011, ISAAC 2011, ...

Experience

  • 2012/04 - present: Rakuten Institute of Technology, Rakuten Inc., Japan.
  • 2009/05 - 2012/03: Research Assistant for Hokkaido University Global COE Project.
  • 2008/08 - 2008/09: Internship at Sony LSI Design Inc.
  • 2008/08 - 2008/08: Teaching Assistant for Open Campus 2008 in School of Engineering Hokkaido University.
  • 2008/04 - 2008/05: Teaching Assistant for Teaching programming in C.
  • 2007/11 - 2007/12: Teaching Assistant for Teaching information theory and information mathematics.
  • 2007/08 - 2007/08: Teaching Assistant for Open Campus 2007 in School of Engineering Hokkaido University.