Home‎ > ‎

EDA Tools

 
Currently, all of the EDA tools are installed under the directory of "/usr/cad".

Some of the CIC training documents are available on-line.


License server utility

 lmutil lmstat -c @servername -a (display all information) or   -A (display all active licenses)

Pspice 5280@140.135.106.100
Matlab 27000@140.135.160.1
Xilinx 2100@140.135.12.101
Altera 9700@140.135.12.101


1717@140.126.24.16;27000@140.135.160.1;2100@140.135.12.101





Altera Quartus II

     Altera University Program

Windows

    9700@140.135.12.101

Linux

    You need to setup and configure your environment variables before you can run Altera Quartus and Modelsim properly. Please edit your .cshrc with extra lines shown as follows:
You can also download the altera.csh file to your home directory and source it under c-shell.
The altera.csh file put in server at /usr/cad/altera7.2 , you can also type source /usr/cad/altera7.2/altera.csh.

You should be able to see the Quartus binary located at /usr/cad/altera7.2/quartus/bin/quartus directory when you type which quartus at your command prompt.
The Altera Quartus II GUI will be popped up shortly after you type the following command:



Just in case your Quartus crashes!

If the Quartus® II software crashes, you may not be able to restart the software.  This problem occurs because the software may not properly clean up its environment. Follow these steps to clean up the UNIX or Linux environment:

  1. Run <Quartus II installation directory>/bin/mwcleanup
  2. Kill any processes with names beginning with quartus or mw
  3. Delete the ~/mw directory
  4. Delete the /tmp/mw_<username> directory




Xilinx ISE

 Xilinx University Program

The Xilinx FPGA design suite (V10.1) is installed under /usr/cad/Xilinx/10.1 directory. Currently, we have the "ChipScope", "EDK" and "ISE" for Linux based operating system.

You need to source settings32.sh (bash shell) or source settings32.csh (c-shell) before running the executables of each tool (ChipScope, EDK and ISE)



Xilinx ISE Design Suite 10.1 Software Tutorials

The complete Xilinx ISE 10.1 Design Suite Software Manuals and Help - PDF Collection manuals are highly recommended for reading.

CIC Training Tutorial File (ISE9.1)


 

Verilog XL

 
You  need  source  ldv.csh(c-shell)  and  source license.csh(c-shell).
 
 
 
Assuming yout have two Verilog files , test.v and tb_test.v . Please compile these two Verilog files by using the following command . These two Verilog files are without any errors . You can invoke simvision to display the waveforms of your design.
 
 
You can also type simvision to open simvision to display the waveform of your design.
 
 
  

 

Cadence NC-Verilog

The NC-Verilog software is installed under /usr/cad/cadence/LDV/cic_setup directory.

You need source ldv.csh(c-shell) and source license.csh(c-shell).



The user’s document for the SimVision can be viewed by typing the command as follows:



Assuming you have two Verilog files, full_adder.v and test_full_adder.v. Please compile these  two Verilog files by using the following command. The simulation will be ended with the message showing “Simulation complete via $finish(1) at time ... NS ". You can invoke simvision to display the waveforms of your design.


You can also type nclaunch new to open a new Graphical User Interface.





Synopsys Logic Synthesis (Design Compiler/ DesignVision)

Synopsys Design Vision is the newest GUI with lot of performance improvements. The tool is capable of
handling larger design with less memory requirement. For example, in a 800k-gate design, XG mode only
consumes 2.8Gbyte of memory where non-XG mode needs 4.8Gbyte of memory.

Please double check you have a file named “.synopsys_dc.setup” in your home directory.


The Design Compiler / DesignVision software is installed under /usr/cad/synopsys/CIC directory.

You need source license.csh and source synthesis.cshrc before using this software.





Synopsys VCS 


 
 

 
Verdi




Synopsys Hspice

(請 上億 編輯)

HSPICE 為Synopsys公司所有之電路模擬軟體,其功能包含電路階層之交、直流及暫態分析,參數變異之Monte-Carlo分析等。HSPICE的語法與一般SPICE的描述格式相容。可應用於各類數位、類比積體電路設計的特性分析上。在所支援的電晶體模型方面,包含Modified-BSIM1的 level 28 及BSIM3V3的level 49模型等。AvanWaves為一模擬資料的圖形分析處理界面,可顯示及處理Synopsys HSPICE的各類模擬結果。
Hspice Tutorial (adopted from CIC)


 
 
Synopsys CosmosScope
 
(請 思齊 編輯)
 
由於Hspice內的示波軟體Avanwave不支援Linux環境,因此欲分析Spice產生的波形,須使用Synopsys的另一套波形軟體CosmosScope來顯示Spice產生的波形檔。
 
 


Synopsys Astro


Synopsys Astro is the Automatic Place and Route (PnR) tool from Synopsys. Aside from PnR, it can also perform Verification and can also generate back-annotation scripts. For more details, see the Astro User Guide. The Astro version used in this tutorial is Z-2007.03-SP3. Before you begin with the tutorial, you need to have a netlist output from the synthesis tool (<synthesized_design>.v). For more information on how to synthesize a design, see the Design Vision Manual.

After the PnR process, you should be able to produce two files which can be used for simulation:

  • <layout>.v – the hierarchical netlist output from Astro.
  • <delay>.sdf – the standard delay file for the layout.

Astro Tutorial (Edited by Alfonso Cesar Albason )

Synopsys NanoSim

you have to source four important shell scripts under c-shell for Synopsys and Spring-soft license and environment setup.

$ csh

$ source /usr/cad/synopsys/CIC/lincense.csh

$ source /usr/cad/synopsys/CIC/nanosim.cshrc

$ source /usr/cad/synopsys/CIC/vcs.cshrc

$ source /usr/cad/spring_soft/CIC/verdi.cshrc




Laker

Laker 為思源科技公司 (SpringSoft) 所有之積體電路佈局軟體,其功能除具備一般傳統佈局編輯器 (Layout Editor) 在圖形數據輸入和修改方面的所有基本能力外,更增加一些較高效率的新功能,像是對位 (align)、動態式測距 (distance) 、Net Tracer等;另外,Laker 軟體具有許多自動化特性如:Magic Cell、Rule-Driven、Netlist In (Netlist translate to Layout) 等,以協助學術界方便且快速的完成 layout 編輯。
Synopsys Astro (請 上億 編輯)
Laker tutorial (adopted from CIC)



Mentor Graphic ModelSim

Linux

The ModelSim is installed under  /usr/cad/mentor/CIC/  directory.
You need source license.csh and source modelsim.cshrc before using this software.

Windows

LM_LICENSE_FILE

1717@140.113.202.153


(others to be updated)
ModelSim教學
 
 License Server name
(host_name)           license server IP    地區
-------------------   -----------------    ------------------------------------------
lsntu3                  140.112.20.56        台北市,新北市,基隆市,宜蘭縣,花蓮縣
-------------------   -----------------    ------------------------------------------            
lsncu3                  140.115.71.53        桃園縣
-------------------   -----------------    ------------------------------------------    
lsnctu3               140.113.202.153      新竹縣市,苗栗縣,澎湖縣,金馬縣,連江縣
-------------------   -----------------    ------------------------------------------
lsnchu3                  140.120.90.45        台中市,南投縣,雲林縣,彰化縣
-------------------   -----------------    ------------------------------------------
lsncku3                  140.116.216.91       嘉義縣市,台南市,高雄市,屏東縣,台東縣
=====================================================================================
            
 
Ċ
YK CYCUEE,
Apr 6, 2009, 3:39 AM
ą
YK CYCUEE,
Aug 10, 2011, 12:07 AM
ą
YK CYCUEE,
Aug 10, 2011, 12:21 AM
Comments