Welcome to Shijing Yao's Homepage


Address: 205 Cory Hall #1722, Berkeley, CA 94720, United States

Tel: +1-510-710-1949

Email: yaoshijing@berkeley.edu


University of California, Berkeley, August 2008 - Present
Ph.D. Candidate, Advised by Prof.Chenming Hu, Electrical Engineering and Computer Science GPA: 3.88/4.0

Tsinghua University Beijing, China, August 2004 - July 2008
Bachelor of Engineering, Electrical Engineering and Computer Science GPA: 90/100

Awards:               First-Class Comprehensive Prize Fellowship, Tsinghua University, 2007
                            Second Prize in the 13th College Physics Contest in Beijing, 2005
                            Excellent Performance in the 5th Electronic Design, Tsinghua University, 2006

Leadership:        Class Representative to the Student Council, Sept. 2006 -Sept. 2007
                            Study Committee Chair, Sept. 2004 – July 2005

Research Experience:

Graduate Student Researcher: Bsim Group, Electrical Engineering and Computer Science, University of
California, Berkeley,
Sept. 2008 --- Jun. 2009
• Global Extraction Procedure for Bsim Common Multi- Gate FinFET Compact Model

Research Assistant:CAD Research Center, Institute of Microelectronics, Tsinghua University--- Beijing, China, Jul.  2007 --- Sept. 2007
•  Modeling of Non-Quasi-Static Effects in RF MOSFET by Model Order Reduction

Research Assistant: Division of Micro/Nano Devices and Systems, Institute of Microelectronics, Tsinghua University --- Beijing China, Sept. 2006 --- May.  2007
•  Study of Casimir Effect in NEMS: Resonance Devices

Research Assistant:CAD Research Center, Institute of Microelectronics, Tsinghua University --- Beijing, China, 

Dec. 2007 --- Jul. 2008
•  Placement and Routine: Parallel Algorithm based on GPU

Internship: Dongfeng Peugeot Citroen Automobile Company ---Wuhan, China, Jul. 2005 ---Aug. 2005
•  Mechanical Design for YAMAHA FEEDER using Auto CAD

Project & Experiment Designer:
•  Traffic-light-Control System, 12/2005 & Data Adapter based on FPGA, Electronic Lab Center, 08/2006;
•  32bits_UCBerkely_Carrybypass_adder, 12/2006 & Broadband fully-differential Cascode OPA, 06/2007;
•  Digital Voltage Measurer, Electronic Lab Center, 08/2006;

•  C++ Program Training & 32bits_RISC---MIPS by Jsim, 10/2007;
•  Electronic Workmanship Practice & Digital Logic and Analog Circuit Experiment, 09/2005—12/2006.


 1. S. Yao,Y. Deng,Z. Yu, "Balanced truncation on empirical gramians for model-order-reduction of Non-Quasi-Static effects in MOSFETs", Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference, On page(s): 309-312 

 2. S. Yao, T. H. Morshed, D. D. Lu, S. Venugopalan, A. M. Niknejad and C. Hu, "A Global Parameter Extraction Procedure for Multi-gate MOSFETs", International Conference on Microelectronic Test Structures, submitted.

3.  D. D. Lu, C.H. Lin, S. Yao, et al, "Design of FinFET SRAM Cells using a Statistical Compact Model", SISPAD 2009, accepted.

Diversity:  ( click me for highlight! )

◆  Haas School of Business, University of California, Berkeley, Cars 2.0 Investigator February 2009 - May 2009
    Electric Vehicle SUV Rollout and Breakeven Scenario Strategy

◆  Summer Service to Pingtang, Guizhou Province: T.A. & Journalist ---- Jul. 2006
◆  Junior Achievement Career Go Course Trainee, Oct. 2007
◆  Outward Bound: Student Leader and Organizer ---- Mar. 2006
◆  Cultural Heritage Survey to Hutong and Courtyard Houses in Beijing: Student Leader ---- Apr. 2007


•  Experience with C, C++, Verilog, Verilog-A, VHDL, Matlab, Assembly Language
•  Familiar with EDA tools: Spice, Maxplux Ⅱ, Quartus Ⅱ, ADS


Chinese(Native), English


Sports, Violin, Light Music, Photograph