Research

In general, I have a broad interest in building hardware, especially in designing VLSI circuits, novel microarchitectures for emerging applications and acceleration hardware for AI/machine learning. 

During my PhD career at the University of Virginia, my main dissertation research topics were in reliability and power (or energy) aspects. Also, I have been involved in several other research projects in the areas of  new micro-architectures, CAD Design Methodologyon-chip power delivery and IoT Security & Reliability. 

1. Reliability (Wearout, Cross-layer Resilience)

Project: Cross-Layer Accelerated Self-Healing and Circadian Rhythms for Resilient Digital Circuits and Sys-
tems (Reliability, Frontend Design, Backend Design, Testing, Modeling, FPGA, Tapeout)

Description: This work proposed to utilize recovery as a new direction of mitigating wearout issues. We demonstrated improvements in lifetime as well as the power, performance and area (PPA) metrics of future electronic systems by the use of extensive accelerated (High Temperature) and active (Negative Voltage, reverse current, etc.) recovery methods for wearout mechanisms such as bias temperature instability (BTI) for CMOS and Electromigration (EM) for interconnects.

My Role:
  • Developed accelerated and active recovery techniques that lead to more than 70% recovery (including irreversible part) within only 1/4 of the stress time for both BTI and EM wearout
  • Reduced the necessary wearout design margin by more than 98% and improved the average performance by more than 9% through circadian rhythm-like accelerated and proactive recovery 
  • Proposed a wearout-free system which integrated the accelerated self-healing techniques cross the layers of the system stack (circuit to system level)
Publications:
[5] X. Guo, M. Stan, Enabling Wearout-Immune BEOL and FEOL with Active Rejuvenation," IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), in conjunction with ICCAD, Austin, TX, November 2016.
[4] X. Guo, M. Stan, "Towards Wearout-Free Systems: A Self-Healing Strategy Enabled by Accelerated and Active Recovery,Accepted by SRC TECHCONAustin, TX, September 2016.
[3] X. Guo, M. Stan, "Implications of Accelerated Self-Healing as a Key Design Knob for Cross-Layer Resilience", Integration, the VLSI Journal, vol. 56, pp. 167-180, 2017.
[2] X. Guo, M. Stan, "Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenation," Proc. of the ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Macau, China, January 2016.
[1] X. Guo, W. Burleson, M. Stan, "Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques," In Proc. of ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2014.

Project: Circuit-level Wearout-aware Design Techniques and Methodology

Description: This project develops the cross-layer optimization framework with a focus on wearout-aware design at the circuit level. The goal of this project is to develop sensors, novel circuit structures to enable the accelerated and active recovery. Also, we propose a SPICE-compatible model which integrated the recovery behaviors that can be plugged into circuit simulators to enable the design space exploration for reliable design. The success of the model will lead to the new design methodology, like design for accelerated recovery (DFAR) or Power- and Wearout-aware co-design methodology, and enable the optimized scheduling algorithms that trade off between lifetime and other metrics. The last part of the project is to investigate the impact of wearout (or recovery) in the low-voltage domain for IoT applications.

Summary:
  • Sensing: Developed a novel type of all-digital small wearout sensor IP (only 15 transistors) that were able to track both wearout and recovery and detect path-reranking simultaneously (taped out in 130nm bulk)
  • Power Gating: Developed low-overhead power-gating and novel circuit structures to enable both BTI and EM active recovery (taped out in 28nm FDSOI)
  • Modeling: Co-developed a SPICE-compatible transient BTI model with RC components which capture the accelerated and active recovery behaviors
  • Low Power: Ran circuit level simulations to investigate the impact of wearout in low-voltage domain by considering together with other variations in IoT applications
Publications:
[2] X. Guo, M. Stan, Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery," submitted.
[1] X. Guo, M. Stan, "MCPENS: Multiple-Critical-Path Embeddable NBTI Sensors for Dynamic Wearout Management," Proc. of 11th IEEE Workshop on Silicon Errors in Logic–System Effects (SELSE-11), pp. 116-121, Austin, TX, April 2015. 

2. Low Power, Energy Efficient Design

Project: A 14nm Energy-efficient and Resilient RISC-V based SoC (Collaborated with IBM)

Description: In this work, we built a low voltage SoC (5-stage pipeline in order core + Accelerators + Interface) based on the RISC-V infrastructure. The main goal of this project is to look into the voltage noise issues, cross-layer sensing and resilience aspects of the advanced technology node.

Summary:
  • Led the chip design and tapeout effort and coordinated with the industry collaborators
  • Created and enhanced the RTL to GDS II flow (including low power UPF flow, SRAM generation, sensor macro integration, etc.) with 14nm FinFET technology in Synopsys environment 
  • Involved in integrating cross-layer sensors and actuators feedback loop in the system
  • Explored the resilience aspect of the design and performed comprehensive wearout analysis 
  • Developed a design flow that includes stack height as a design knob for finFET design by utilizing its immunity of body effect
Publications:
[1] X. Guo, Q. Qin, M. Stan, "Stack Height Analysis for FinFET Logic and Circuit," Advanced VLSI Class Project ReportMay 2015. (pdf)

Project: A Recursive Structure Power Aware Block based Imprecise Multiplier (PABAIM) (Collaborate with Eric Zhang)

Description: In many applications such as multimedia and DSP, 100% accuracy is most of the time not a strict requirement due to the inherent limitation of human-beings and the inevitable occurrence of errors in VLSI technology. By introducing accuracy as an additional design parameter, we can achieve a new Pareto optimal surface for the multiplier design. This work proposes a novel recursive structure block-based Wallace tree multiplier with the capability to tune its accuracy based on the precision and power requirements. By tuning the fidelity design “knob”, we show that the 32 bit implementation of the proposed imprecise multiplier can achieve an average power savings up to 47% and 10% improvement in latency compared to a convectional Wallace tree multiplier. A case study on JPEG compression algorithm demonstrates the promising application of such multiplier design.

Summary:
  • VHDL implementation and simulation of 8 by 8 bit PABAIM
  • Test verification of each design
  • Power and Performance simulation in cadence
  • Zero detection and precision control circuit implementation in Cadence
  • Taped out in 130 bulk technology in 2013
         Publications:
         [1] H. Zhang, X. Guo, M. Stan, "A Recursive Block based Power Aware Imprecise Multiplier," VLSI Class Project Report, December 2012. (pdf)

3. Novel Architectures for Emerging Applications (Center for future architectures (C-FAR))

Project: Dual-Data Rate Transpose-Memory Architecture for Signal Processing Systems

Description: 

Summary:
  • ASIC implementation (RTL to GDS) of the novel architecture and power/performance analysis with primetime and primetime PX tools.
Publications:
[1] M. El-Hadedy, X. Guo, M. Margala, M. Stan, K. Skadron, "Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems". Journal of Signal Processing Systems (JSPS)(2016): 1-18.

Project: Area-Efficient VLIW-based Programmable Processing Element for Crypto-Systems

Description: 

Summary:
  • ASIC implementation (RTL to GDS) and power/performance analysis with primetime and primetime PX tools.
Publications:
[2] M. El-Hadedy, X. Guo, M. Stan, K. Skadron, \Area- and Power-E.cient VLIW Programmable Processing Element for IoT Crypto-Systems," submitted.
[1] M. El-Hadedy, X. Guo, M. Stan, K. Skadron, "Area-Efficient VLIW-based Programmable Processing Element for Crypto-Systems,Accepted by SRC TECHCONAustin, TX, September 2016. (pdf)


Previous Research Highlights (M. S at the University of Florida)                                                                                   August, 2010 - May, 2012

Project: GaN High Electron Mobility Transistor Based Sensors for Medical Applications   

Description: GaN materials has Wide direct bandgap (3.4eV), Large critical electric field (3MV/cm), high electron mobility (Compared to Si), high electron saturation velocities and good thermal conductivity. Additionally, we can fabricate HEMT with other related materials. So it is a good candidate for sensing application. This project is collaboration of ECE, MSE and CheE department.

My Work 
Extracted the device model and collaborated with Chemical Engineering dept. for AlGaN/GaN HEMT fabrication
Designed the detection circuit to amplify sensor signals through excellent sensitivity of Gateless GaN transistors

Undergraduate Research  (B. S at Xidian University)                                                                                                      August, 2006 - June, 2010

Project: Design and build the testing system for Solid State Fuel Cell based on LabVIEW virtual instruments

Description: Solid oxide fuel cells (SOFCs) receive considerable interests nowadays, By analyzing the working principle, discreteness and structure of single SOFC. In this project, I establish the electrode mathematical model by the software Matlab/Simulink, the model considers all forms of polarization losses include activation polarization, ohmic polarization and concentration polarization. Then the result is fed to LabVIEW test environment and verified.

My Work 
Established the electrode mathematical model by Matlab/Simulink tools considering all polarization losses
Realized the possibility of SOFC testing system based on virtual platforms and saved expenses

Class-related projects are under Graduate Courses section.
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