ISCA 2013                                                                                                                           


Intel® Xeon Phi™, HW architecture and programming model


Gus Espinosa ,Toni Juan, Jesus Corbal and Robert Geva

Targeted audience

The tutorial is intended for practitioners, researchers and students interested in writing efficient, parallel code to exploit the compute power in the Intel® Xeon Phi™ coprocessor.


Intel® Xeon Phi™ is a new many core product line from Intel combining general purpose computing and parallel computing in a coprocessor model. The HW provides many Intel Architecture cores integrated into a shared memory system with simultaneous multi-threading per code and wide vectors.

The tutorial is composed of two main parts: the HW architecture and the programming model. In the first part, we will show the HW architecture and focus on the necessary characteristics to understand performance, be able to design for performance and understand performance analysis of workloads executing on the Xeon Phi coprocessor. In the second part we will show the fundamentals of the programming model. The Xeon Phi can be used in multiple ways. One of these ways is to execute applications natively. In this usage, the programming model is the same as any CPU, and the remaining challenge is to write efficient parallel code. The Xeon Phi coprocessor can also be combined with a Xeon processor to form a heterogeneous system, where both are executing portions of a parallel program and communicate with each other thru the system bus. The tutorial will show the capabilities of the Intel compiler supporting the heterogeneous programming model. The offload capabilities are currently being standardized in the OpenMP® ARB.


  1. Intel® Xeon Phi™ architecture
    1. Core architecture
    2. VPU / Vector ISA fundementals
    3. L2 / Ring architecture
    4. PCIe interface
  2. Intel® Xeon Phi™ coprocessor programming model
    1. Emphases in parallel programming for Intel Architecture
    2. Shared memory parallel programming for Xeon and Xeon Phi
      1. Shared memory parallelism with OpenMP
      2. Composable parallelism with work stealing
      3. Divide and conquer programming with Cilk™ for cache efficiency
    3. Vector programming
    4. Data layout
      1. Data alignment considerations
      2. Array of Structures vs. Structure of Arrays
    5. Heterogeneous programming with Xeon and Xeon Phi


One day: start time 9:00, end time 6:00.


Robert Geva is a Principal Engineer at Intel's Software and Services Group. Robert joined Intel in 1991 and has since developed an expertise in compilers and performance analysis and tuning for microarchitectures. Robert has worked on compiler optimizations for a variety of Intel microprocessor based systems, including the 80486, the Pentium® Processor, the Pentium® Pro Processor, Itanium®, the Pentium® 4 and Pentium® M and Core™ II Duo. Currently, Robert is an architect in the development products division responsible for driving language extensions and programming models for parallel and heterogeneous programming. Robert has been involved with the development of Intel Cilk™ Plus and the offloading model for Intel® Xeon Phi™. Robert has Bachelor of Arts and Master of Science degrees from the Technion-Israel Institute of Technology.

Gus Espinosa is a Senior Principal Engineer and Director of the MIC Architecture Development group at Intel's Visual and Parallel Computing Group. Gus joined Intel in 1991 and has held a variety of technical and leadership roles in architecture and design. He has worked on many of Intel's major microprocessor designs since the 486 generation and served as chief architect of several Intel Pentium® III and Intel Pentium® 4 processors. He currently leads the team responsible for the architecture development of the Knights family processors in the MIC organization. His areas of expertise are in computer architecture, processor microarchitecture, microcode, and performance analysis. Gus holds a Bachelor of Science degree in Electrical Engineering from Cornell University and a Master of Science degree in Computer Engineering from Boston University.

Toni Juan is a Principal Engineer with more than 11 years of experience at Intel and currently he is the Uncore Architect for the Intel® Xeon Phi™ family of products. His expertise and contributions span across memory hierarchy, memory controllers, on-die interconnect, memory coherence and performance modeling.  Toni holds a Master of Science degree in Computer Engineering  and a Doctor of Philosophy degree in Computer Engineering from the Universitat Politecnica de Catalunya (UPC).

Jesus Corbal is a Principal Engineer working in the MIC Architecture Development group in Intel's Visual and Parallel Computing Group.  Jesus joined Intel in 2002 and has since developed an expertise in vector microarchitectures and ISA SIMD extensions.  Jesus has worked on advanced development projects related to adding true vector capabilities to contemporary processors, resulting in the introduction of SIMD ISA extensions such as Intel® AVX (Advanced Vector Extensions) and Intel® Xeon Phi™ KCi (Knights Corner Instructions).  Currently, Jesus is working as a product architect on the next generation Xeon Phi™ product, focusing on high performance vector hardware and instruction capabilities.  Jesus has a Master of Science degree in Electrical Engineering  and a Doctor of Philosophy degree in Computer Engineering from the Universitat Politecnica de Catalunya (UPC).

Related links