I am currently a principal architect at Nvidia.
In the past I was a senior architect at Intel in Santa Clara. Prior to that I was at Intel-Labs Barcelona, working as a research scientist, and part of the ARCO group.  While at ARCO I was co-advising Jose Maria Arnau along with Joan Manuel Parcerisa.

I finished my Ph.D. at the University of Edinburgh on August 2009. During my last year in Edinburgh  (2008-2009) I was also a research assistant for the iTLS project, which is a joint work between the University of Edinburgh and the University of Manchester.

My advisor was Marcelo Cintra, and I was part of the Compiler and Architecture Design group (CArD). For my Ph.D. thesis my main focus was on how to combine different speculative execution models.

Before joining the University of Edinburgh, I obtained my Diploma in Electrical and Computer Engineering from the University of Patras, Greece. My advisor there was Stefanos Kaxiras.


My main research area is Computer Architecture, however I am also interested in related areas such as compilation and OS. More specifically, the last few years I have been working in the area of high performance architectures while before that I was looking at low power cache design.

Here is a fancy pictorial description of my thesis:

Wordle: Mixed Speculative Multithreaded Execution Models



  • Microarchitectural Design for TLS Systems. National Technical University of Athens, Electrical and Computer Engineering Department, 2008.