王世豪 🤪 Shihao Wang

Publications

1. Energy-efficient Scheduling Method with Cross-loop Model for customized CNN Accelerators,

2. Kaiyi Yang, Shihao Wang, Jianbin Zhou and Takeshi Yoshimura,

3. IEEE International Symposium on Circuit and Systems (ISCAS), 2017, accepted.

4. Chain-NN: An Energy-Efficient 1D Chain Architecture for Accelerating Deep Convolutional Neural Networks,

5. Shihao Wang, Dajiang Zhou, Xushen Han and Takeshi Yoshimura,

6. Design, Automation and Test in Europe, (DATE), 2017. [Link]

7. CNN-MERP: An FPGA-Based Memory-Efficient Reconfigurable Processor for Forward and Backward Propagation of Convolutional Neural Network,

8. Xushen Han, Dajiang Zhou, Shihao Wang and Shinji Kimura,

9. IEEE International Conference on Computer Design (ICCD), 2017. [Link]

10. An 8K H.265/HEVC Video Decoder Chip with a New System Pipeline Design,”

11. Dajiang Zhou, Shihao Wang, Heming Sun, Jianbin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, and Satoshi Goto, “

12. IEEE Journal of Solid State Circuits (JSSC), Jan. 2017. [Link]

13. VLSI implementation of HEVC motion compensation with distance biased direct cache mapping for 8K UHDTV applications,

14. Shihao Wang, Dajiang Zhou, Jianbin Zhou, Takeshi Yoshimura, and Satoshi Goto,

15. IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), 2016. [Link]

16. A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8K Ultra-HD TV Encoding,

17. Jianbin Zhou, Dajiang Zhou, Shihao Wang, Shuping Zhang, Takeshi Yoshimura, and Satoshi Goto, 

18. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2016. [Link]

19. A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications,

20. Dajiang Zhou, Shihao Wang, Heming Sun, Jianbin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, and Satoshi Goto,

21. IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 266-267, February 2016. [Link]

22. High performance VLSI architecture of H.265/HEVC intra prediction for 8K UHDTV video decoder,

23. Jianbin Zhou, Dajiang Zhou, Shihao Wang, Takeshi Yoshimura, and Satoshi Goto,

24. IEICE Transactions on Fundamentals, Vol. E98-A, No. 12, pp. 2519-2527, December 2015. [Link]

25. Unified parameter decoder architecture for H.265/HEVC motion vector and boundary strength decoding,

26. Shihao Wang, Dajiang Zhou, Jianbin Zhou, Takeshi Yoshimura, and Satoshi Goto,

27. IEICE Transactions on Fundamentals, Vol. E98-A, No. 7, pp. 1356-1365, July 2015. [Link]

28. Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder,

29. Shihao Wang, Dajiang Zhou, Jianbin Zhou, Takeshi Yoshimura and Satoshi Goto, 

30. Pacific Rim Conference on Multimedia (PCM), Kuching, Malaysia, December, 2014.. [Link]

31. Motion compensation architecture for 8K UHDTV HEVC decoder,

32. Shihao Wang, Dajiang Zhou, and Satoshi Goto, 

33. IEEE International Conference on Multimedia and Expo (ICME), Chengdu, China, July, 2014. [Link]

Academic Experience

2016 – 2017 | Deep Convolutional Neural Network (CNN) Accelerator

    • Developed a novel 1D chain architecture based chip-level CNN accelerator, named Chain-NN. This work has been accepted by DATE 2017, a top design automation conference.  Its energy efficiency and throughput performance surpass all the existing state-of-the-art works. 

    • Developed an FPGA-based demonstration system of Chain-NN.

    • Participated in researching on optimizing CNN algorithms and architectures for FPGA platforms.  

2012 – 2015 | HEVC Decoder Chip for 8K Ultra High Definition TV

    • Core participant (the 2nd in contribution) for the world first HEVC 8K decoder chip. The chip was presented at the No.1 integrated circuits conference ISSCC and won the conference’s highest honored Outstanding Far East Paper Award.

    • Conducted algorithm- and architecture- level development of key components of the chip including cache, motion compensation and parameter decoder.

    • Conducted system-level FPGA designs for chip’s verification and real-time demonstration.