Program

  •  8:30 - 8:40 Opening Remarks

Keynote Session

  •  8:40 - 9:30 : Torsten Hoefler Scientific Benchmarking of Parallel Computing Systems

Session 1

Invited Talks

  • 9:30-10:00 Brad Chamberlain A Language Designer's Perspective on Benchmarking Suites and Competitions

  • 10:00-10:30 Break

  • 10:30-11:00 David Bailey New ways to fool the masses

Session 2

Invited Talks

  • 11:00-11:30 Laura Carrington Using Machine Learning and Benchmarks to Understand the Memory Hardware Sensitivity of HPC Applications
  • 11:30-12:00 Antonio Gomez Benchmarking of Petascale Systems at TACC
  • 12:00-13:30 Lunch (attendees on their own)

Program Details

Keynote Session

Author

Torsten Hoefler (ETH Zürich)

Short Bio

Torsten is an Assistant Professor of Computer Science at ETH Zürich, Switzerland. Before joining ETH, he led the performance modeling and simulation efforts of parallel petascale applications for the NSF-funded Blue Waters project at NCSA/UIUC.  He is also a key member of the Message Passing Interface (MPI) Forum where he chairs the "Collective Operations and Topologies" working group.  Torsten won best paper awards at the ACM/IEEE Supercomputing Conference SC10, SC13, SC14, EuroMPI'13, HPDC'15, HPDC'16, IPDPS'15, and other conferences.  He published numerous peer-reviewed scientific conference and journal articles and authored chapters of the MPI-2.2 and MPI-3.0 standards. He received the Latsis prize of ETH Zurich as well as an ERC starting grant in 2015. His research interests revolve around the central topic of "Performance-centric System Design" and include scalable networks, parallel programming techniques, and performance modeling.  Additional information about Torsten can be found on his homepage at htor.inf.ethz.ch.

Abstract

Measuring and reporting performance of parallel computers constitutes the basis for scientific advancement of high-performance computing (HPC). Most scientific reports show performance improvements of new techniques and are thus obliged to ensure reproducibility or at least interpretability. Our investigation of a stratified sample of 120 papers across three top conferences in the field shows that the state of the practice is not sufficient. For example, it is often unclear if reported improvements are in the noise or observed by chance. In addition to distilling best practices from existing work, we propose statistically sound analysis and reporting techniques and simple guidelines for experimental design in parallel computing. We aim to improve the standards of reporting research results and initiate a discussion in the HPC field. A wide adoption of this minimal set of rules will lead to better reproducibility and interpretability of performance results and improve the scientific culture around HPC.


Session 1

Author

Brad Chamberlain (Cray Inc.)

Title

A Language Designer's Perspective on Benchmarking Suites and Competitions

Abstract

As a designer and implementer of programming languages for HPC, the existence of standard benchmark suites and competitions has been invaluable to my work. In this talk, I'll describe my experiences with some key suites and styles of benchmarks, including the NAS Parallel Benchmarks (NPB), HPC Challenge competition (HPCC), DOE proxy applications, Computer Language Benchmark Game, and Intel's Parallel Research Kernels (PRK). In doing so, I'll describe what I view as the strengths and weaknesses of these approaches. I'll also outline the characteristics of my ideal, imagined benchmarking framework for HPC.

Author

David Bailey (LBNL)

Title

New ways to fool the masses

Session 2

Author

Laura Carrington (SDSC)

Title

Machine Learning and Benchmarks to Understand the Memory Hardware Sensitivity of HPC Applications

Abstract

In the pursuit of improving energy efficiency in HPC systems, often the proposed solutions impact the memory sub-system. To identify the code regions that are the most impacted and to guide them in developing mitigating solutions, system designers and application developers alike would benefit immensely from a methodology that allowed them to identify the types of computations that are sensitive to these memory sub-system changes and to precisely identify those regions in their code that exhibit this sensitivity. This talk introduces a methodology that utilizes a set of computational benchmarks and machine learning techniques to identifying the properties in computations that are associated with sensitivity to changes in the memory sub-system. By extracting those same properties from HPC applications one can utilize the ML models to identify these sensitivities in the different computational phases of a large-scale HPC application.

Author

Antonio Gomez (TACC)

Title

Benchmarking of Petascale Systems at TACC

Abstract

The Texas Advanced Computing Center offers some of the most powerful systems in the Open Science community in the US. The variety of codes and communities supported by TACC requires of a large number of codes and benchmarks to be evaluated before a system can go into production. Also, common workloads in the system are considered when designing future systems to ensure that they will satisfy the requirements of a vast user base. Considerable efforts are devoted to evaluate new processors and architectures and to understand how potential designs can affect those common scenarios.
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Jun 29, 2017, 10:55 AM
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Jun 29, 2017, 1:36 PM
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Jun 29, 2017, 11:07 AM
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Jun 29, 2017, 10:57 AM
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Piotr Luszczek,
Jun 29, 2017, 10:48 AM
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