Analog Shift Register

An Analog Shift Register (ASR) module is essentially a sophisticated kind of Sample and Hold (S&H). It will, at every clock pulse, sample the CV value of the input and makes it available at the first output. So far, it's a basic S&H. The thing is, a ASR has many outputs, and what it does is that at every clock pulse, it shifts the value of output 1 to output 2, and likewise, value of output 2 gets to output 3. So at every clock pulse, the CV values gets' shifted to the next output with the exception of output 1 that samples a new value at every clock ( 

While the central importance of the California Institute of the Arts (CalArts) is agreed, the exact origins of the ASR are debatable. In one account, Stan Levine ( appears to suggest that the module originated in the synthesizers of Serge Tcherepin ( A schematic and block diagram of the Serge ASR circuit can be found in the September/October 1976 issue of Synapse ( 

"The ANALOG SHIFT REGISTER is a sequential sample and hold module for producing arabesque-like forms in musical space. Whenever pulsed, the previously held voltage is sent down the line to three consecutive outputs to produce the electrical equivalent of a canonic musical structure." (

However, another (likely earlier) ASR design appears in the Fortune Modules created by Fukushi Kawakami during the early 1970s (see below). The Fortune Modules were not mass produced like the designs of Serge, but instead created for the composer Barry Schrader as a compliment to the Buchla 200 series ( Intended to do things that would have otherwise been difficult or impossible on the 200 series, these four modules featured in every piece made by Schrader from 1972 to 1985 (

front panel of the Fortune Modules Analog Shift Register
Fortune Modules - Analog Shift Register - front panel

Fortune Module - Analog Shift Register - block diagram
Fortune Modules - Analog Shift Register - block diagram

Ken Stone's CGS34 ( a contemporary ASR design that replicates the functionality of the 1970s Serge design (using a different circuit and modern components). He describes its working as follows:

"The ASR is nothing more than a 4 stage analog memory. Each cell of this memory is a capacitor, followed by a buffer. Addressing each stage of this in turn is half of a 4052 4 pole analog switch. As each cell is addressed, it is forced to follow the incoming voltage. The cell remains connected to the incoming voltage for a full clock cycle, giving it ample time to reach the correct level. At the same time as this is happening, there are three other 4 pole analog switches that are pointing to each of the other three cells. The first of these points to the cell filled the previous clock cycle, the second to the cycle before than, and the third to the one before that. As such, once each cell is filled, it remains that way for 3 clock cycles, then is filled with a new voltage on the fourth. The other three cells are cycled in turn to the 1st, 2nd and 3rd outputs. The TL071 and 4024 form the clock pulse to address converter. The remaining circuitry is an input buffer and three output buffers designed to adapt the voltage to that suitable for switching by the 4052. The input range of the ASR itself is approximately +/- 10V." (

While its implementation is (in some ways) quite different to its hardware ancestors, the functionality of an ASR can be closely replicated in software.