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In order to increase the quality of wireless transmission, wireless communication systems employ advanced forward error correction codes such as turbo codes and low-density parity-check (LDPC) codes. To achieve smooth transition between turbo and LDPC decoding for different communication standards, we propose a VLSI design of a multi-mode radix-4 soft-input soft-output (SISO) kernel in this paper. The proposed radix-4 SISO kernel composed of three recursive processing elements alternatively employs a radix-4 forward–backward algorithm (FBA) for LDPC decoding and a radix-4 single-binary/double-binary (SB/DB) enhanced max-log- maximum a posteriori algorithm (MAP) for turbo decoding by efficiently sharing computational units. The proposed radix-4 SISO kernel achieves an area reduction of 21.8% when compared with the uncombined SISO kernels for alternatively decoding the turbo and LDPC codes. The proposed radix-4 SISO kernel is verified by implementing it in an ASIC of 0.45 mm2 core area using a 90-nm CMOS process with a maximum area efficiency of 10.65 bits/mm2. In addition, the throughput rates of the LTE and WiMAX schemes for both LDPC and turbo decoding can be achieved by using eight proposed radix-4 SISO kernels.
Publication: IEEE TVLSI 2015 (pdf)
＊Lab Introduction:
VLSI Signal Processing Systems Laboratory (VSPS Lab) was setup in the Department of Electrical Engineering, Yuan Ze University (YZU), in 2010. This lab located in Room 70932, 7th Building at YZU is directed by Dr. Cheng-Hung (Dixson) Lin. The main hardware equipments are workstations and personal computers. The software tools are programming languages (C, MATLAB, Verilog, etc.) and EDA tools (Cadence, Avant !, Synopsys, etc.).
Because of a widespread mobile/portable usage and advances in digital signal processing, there is a constant need for designing systems with vision and prospect of energy-efficient and area-efficient VLSI designs. The aim of our Lab is to develop the theoretical and practical aspects of digital signal processing in new and emerging technologies. We do academic/industrial research on the design and implementation of signal processing systems with low-power, high-speed, and low-area VLSI circuits. A wide range of the research topics is covered within fields of algorithms and architectures, system designs and implementations. Seizing the advantage of IC design and production in Taiwan, every graduate in our Lab is requested to have ability to design IC independently. Thus, the efficient algorithms and VLSI architecture designs are targeted to verify the correctness of theory by using ASIC and FPGA. Nowadays, our Lab can be divided into groups carry on the following research projects separately: (1) developing the prospective Iterative forward error correction codec (e.g. Turbo codes and LDPC codes) for communication/storage systems, and (2) developing the prospective Iterative MIMO receivers for advanced communication systems.
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