Xilinx FPGAs programming using 

Linux shell and Makefile


This HOWTO describes how to install and to use Xilinx design environment in Linux Shell. Using Linux shell based methodology you can significantly speedup full recofigurable digital system design flow: from synthesis up to bitfile downloading.

Example of the new project tree:

|-- Makefile
|-- constraints.ucf
|-- loadbit.sh
|-- rtl
|   |-- 7seg.vhd
|   |-- main.vhd
|   |-- vesamodes.vhd
|   `-- vga.vhd
`-- tmp

Example of constraints.ucf:

NET "rgb<2>" LOC ="R12";
NET "rgb<1>" LOC ="T12";
NET "rgb<0>" LOC ="R11";
NET "hor" LOC ="R9";
NET "ver" LOC ="T10";

Example of loadbit.sh to load bitstream onto Spartan3 FPGA using JTAG Parallel Interface III:

echo $a
cd ~/store/inst/XC3Sprog
./xc3sprog $a/output.bit
cd -



1)Download a full copy of the WebPack installer for Linux from here: http://www.xilinx.com/ise/logic_design_prod/webpack.htm

2)Untar this downloaded file:
tar xf webpack_SFD.tar

3)Run installation:
cd webpack && ./setup

4)You must find settings32.sh in the place where you have installed ISE:
find . -name "settings32.sh"
for example, this file must be somewere in /opt/XilinxISE/10.1/ISE for 10.1 version of the ISE if you have installed it in /opt

5)Now copy this file as root into your /usr/local/bin:
sudo cp settings32.sh /usr/local/bin/startise

6)Open this new file as root:
sudo vim /usr/local/bin/startise

7)Add following lines to the end of the file and save it:
export DISPLAY=:0
exec ise

8)Copy settings32.sh file into ~/Xilinx as settings.sh:
mkdir ~/Xilinx
cp settings32.sh ~/Xilinx/settigns.sh

10) Depending on your Linux Distro you may need some more additional shared libraries, because Xilinx tools require them. Just install following software packages:
sudo aptitude install portmap libmotif3 libstdc++5

Installing and using USB Driver

1) Install required libraries:
sudo aptitude install libusb libusb-dev fxload

2)Download, unpack and make usb cable driver:
wget http://technopedia.org/usb-driver-HEAD.tar.gz
tar xzvf
cd usb-driver

3)Insert path to libusb-driver.so into your ~/Xilinx/settings.h, as well as into /usr/local/bin/startise above "exec ise" line if you plan to use GUI  (we are not):
export LD_PRELOAD=`pwd libusb-driver.so`/libusb-driver.so >> ~/Xilinx/settings.sh

4) Copy USB access rights and different rules:
sudo cp XilinxISE/10.1/ISE/bin/lin/xusbdfwu.rules /etc/udev/rules.d/

5)Copy hex files into /usr/share directory:
sudo cp XilinxISE/10.1/ISE/bin/lin/xusb*.hex /usr/share/

6)Restart udev system:
sudo /etc/init.d/udev restart

7)Check, either all was done successfully with "lsusb" command:
vm@vm-desktop:~$ lsusb
Bus 005 Device 006: ID 03fd:0008 Xilinx, Inc.
Bus 005 Device 001: ID 0000:0000 

4)TODO: impact commands


1)You must follow this simple convention to generate new project:

  • For each project create its own unique directory
    Example: mkdir GPU
  • Place all VHDL or Verilog files of your project in ./rtl directory
    Example: cp *.vhd GPU/rtl
  • Place this Makefile into your directory. Specify your top module variable in this file.
    Example: VHDL_TOP := main
  • Create and edit constraints.ucf file in your directory

2)Edit your source files with your favourite text editor
   Example: vim svga_controller.vhd

3)Work with your design in the shell using following simple commands:

  • make  clean to remove all temporary files
  • make init to create ISE project and settings for synthesis
  • make syn to run synthesis to create Xilinx specific netlist files called NGC files from HDL files
  • make net to run ngbuild, which collects together all of the netlist files in one big heap,building them into a giant flattened netlist of the entire design
  • make map to run mapper, which takes the netlist from ngbuild and maps it to the chosen device architechture by breaking it up into CLB sized pieces
  • make par to run place and root
  • make bit to create a bit file
  • make imp, to run net, map, par, and bit, which are described above

You can simply use make all to follow all this stages utomatically. Usually after you have applied new changes in your HDL files, you will prefer to use firstly make syn, and only if there is no errors in your design you will start make imp. After all this stages are successfully finished you will find a bitstream file output.bit in your directory.

4)Use any from the following tools to upload a bitstream into a FPGA: http://gentoo-wiki.com/HOWTO_Xilinx#Cable_interfaces