Department of Electrical and Computer Engineering, Carnegie Mellon University
Advisor: Prof. Larry Pileggi
Duration: 6/10 - present
The applications of the ADCs with a conversion rate of over 20GS/s are mainly for ultra-high-speed communication systems, such as the 60-GHz wireless transceivers and serial links. To achieve high operation speed with low power consumption, the identical ADCs designed with near-minimum sizes and built-in references can be interleaved in time so as to achieve more parallelism. The dynamic offset calibration alleviates offset and gain mismatch between different channels. The self-aligned buffers are utilized to align channel clocks with the proposed digital calibration algorithm. The randomness of process mismatch is exploited to calibrate comparator offsets and timing skew without resistor ladders and extra capacitors. With on-chip background calibration, the sub-channel ADC and time-interleaved ADC achieve the lowest power consumption and best figure of merit.
Time-Interleaved ADC with Clock Generator
R&D Center, Realtek Semiconductor Corporation, Hsinchu, TaiwanDirector: Chao-Cheng Lee
Duration: 8/05 - 4/10
This project is a fully integrated Analog Front End (AFE), including an on-chip line driver, designed for Discrete Multi-Tone (DMT) based ADSL modems compliant with ITU ADSL, ADSL2 and ADSL2+ standards. It includes a high-performance DAC and ADC, continuous-time channel filters, programmable gain control amplifiers, and other miscellaneous functional blocks for versatile operation modes. This chip requires few external components. It intended to be used with the series processors as part of the ADSL2+ chipset. The project can handle two transmission channels on a balanced 2-wire interconnection: A 512-carrier DMT coding (frequency spacing 4.3125kHz) transforms the downstream channel to a 2.208MHz bandwidth analog signal and the upstream channel to a 276kHz bandwidth signal on the line. Asymmetric data rate of up to 24Mbps downstream and 2.3Mbps upstream can be achieved.
Lab: Semiconductor Technology Application Research (STAR) Lab
Advisor: Prof. Ya-Chin King
Duration: 9/03 - 6/05
A novel photodiode model that better describes the electro optical behavior of a complementary metal–oxide–semiconductor (CMOS) image sensor has been developed. The conventional diode model adopted by Berkeley short-channel insulated-gate field-effect transistor model 3 (BSIM3) suffers from a large discrepancy between simulation and measurement results for CMOS image sensors (CISs). The simulated response exceedingly overestimates the dark signal and is unable to provide the optical response of a CIS pixel circuit. A closed-form photodiode model is proposed in our work. The experimental results demonstrate that this photodiode model can accurately predict the relationship between the diode current and the operation voltage, temperature, incident light intensity and wavelength. Using the novel photodiode model, a more precise environment can be established for performance optimization and system-on-chip simulations in various CIS applications.
CMOS Active Pixel Sensors
Photo Current Modeling
Photo Diode Subcircuit Model
As the development of semiconductor process, the high speed is an advantage of high density chips. As the complexity increases, it also comes the problem of power assumption. So, the chip design of low power will be a hot issue. In this project, we developed a simple CPU according to what we had learned in "computer architecture". We used some CAD tools from higher level, RTL behavior model, performance estimation, circuit synthesis and simulation to the lowest level, layout, to get familiar with the flow of modern VLSI design. After the implementation of the simple CPU, we adapt some steps to control the power. Under the condition of low power, we would develop a new circuit architecture, to get the improvement of performance and optimization of power in the next step. So that the design would be faster and save more power.
Chip Layout of The Low-Power CPU