Cheap peripheral lets you test capacitors
I often take junk apart, just to reclaim its parts. Electronics built in the '70s and '80s are cornucopias of discrete components, waiting to be reused. But, when you desolder a PCB, you run the risk of applying too much heat to the components and ruining them. This isn't too much of an issue with resistors, because a simple multimeter will tell you if it still works. But what about capacitors? How do we test them?
We build a circuit whose behavior depends on the capacitance of our test subject. In particular, we are going to use a 555 timer. Recall from my 555 page that the frequency output from a 555 timer in astable mode is:
f = 1 / [ 0.693 ( C ) (Ra + 2 Rb) ]
If we set up an oscillator, and calculate it's frequency, we can determine the capacitor's value. Recall that my logic analyser can faithfully characterize signals up to 125 KHz (250 Ksamples/sec).
We would like to test resistors whose values range from 1 pF (10-12) to 1 mF (10-3). This is a very large range, and an equally broad range of frequencies (Mega hertz to millihertz) would be observed from the 555. This is fine if you don't mind waiting 100 seconds to get a reading...
If we want to be able to capture the entire range of capacitor values, yet with less of a wait, we going to need to do some hackery. Indeed, all the engineering in this project goes into narrowing that range. The first thing we can do to narrow this range is to use a second capacitor Cn in series with our test capacitor. If we choose Cn = 0.1 uF (10-6), then:
1 pF in-series-with 0.1 uF = (1 pF)(0.1 uF)/(1 pF + 0.1uF) = 1 pF
1 mF in-series-with 0.1 uF = (1 mF)(0.1 uF)/(1 mF + 0.1 uF) = 0.1 uF
This isn't free; we lose some resolution.
It's a real drag that our logic analyser can only sample at 250 Ksamples/sec, as it limits us to measuring signals less than 125 KHz. However, we can increase this range if we measure fractions of a higher frequency, and multiply up. Say that we use a 74HC191 4-bit binary counter as a frequency divider. We can now measure a signal by dividing its frequency by 24 = 16, thus our upper limit is (125 KHz)(16) = 2 MHz.
We want to choose values of Ra and Rb so that the frequency is never greater than 2 MHz. Note that the frequency is greatest with C at it's smallest value, so:
fmax = 2 MHz >> 1 / [ 0.693 ( 1 pF ) (Ra + 2 Rb) ]
(Ra + 2 Rb) >> 1 / [ 0.693 ( 1 pF ) ( 2 MHz ) ]
(Ra + 2 Rb) >> 721.5 KOhms
So, let's choose Ra = 470 KOhm and Rb = 180 KOhm, then:
f( 1 pF in-series-with 0.1 uF ) = 1.74 MHz
f( 1 mF in-series-with 0.1 uF ) = 17.4 Hz
The design (schematic) is powered by the parallel port. Usually, we couldn't get away with that while using a 555, but here we're using MaximIC's ICM7555, which will run off of 2V with very little current, and very small current spikes. The chip is otherwise compatible with a 555.
This circuit contains an oscillator whose frequency is dependant on the test capacitor, and puts in through a frequency divider. If one were to use one of the data acquisition programs from my logic analyser they would see that signal P5 is the highest frequency, P4 is half of the frequency of P5, P3 is half of P4, and so on.
However, if the frequency of P5 is greater than 125 KHz, then P5's frequency would appear as f(P5)/2k for some k>0. We can detect this happening because f( Pn+1 ) < f( Pn ). If that is the case, we use the reading from Pn instead.
This may seem convoluted, but it allows us to keep the oscillator at a higher rate, which means that even with the largest capacitors, we can still measure it in a reasonable period of time.
none yet... ;)