Due date 16
1) In high performance systems, memory must be designed
to meet the demand of high performance processor cores. Describe how
the use of i) caching and ii) memory interleaving contributes towards
meeting the processor demand. iii) Compare low-order and high-order
interleaving and its potential benefits. (5 marks)
the segmented virtual memory model and explain how in that model a
logical address specified in an instruction is translated into a
physical address during instruction execution. (5marks)
Using an illustrative diagram, describe the organization and
operation of a superscalar processor that employs shelved
instruction issue. (5 marks).
the concept of register renaming. Using an example instruction
sequence, demonstrate that it solves the problem of anti-dependency.
Given that A, B and C are three arrays each of size 100,000 floating
point numbers, compare the times is takes to complete the addition
C=A+B using a) scalar arithmetic b) pipelined vector processing and
c) spatial parallel processing (i.e. array processor concept).
an array processor with 8 PEs. Compare two interconnection design
options known as 2-D near-neighbour
respectively with regard to the parameters known as network diameter,
probability of blocking. (5 marks)